Mitsubishi Electric Develops High-Frequency Synchronous SRAM with Dramatically Reduced Soft Error Rate.

SAN FRANCISCO--(BUSINESS WIRE)--Feb. 15, 1999--

New Technology Achieves Operating Frequency of 500 MHz and Is 100

Times More Resistant to Cosmic-Ray-Induced Soft Errors than

Conventional SRAM

Mitsubishi Electric  Corporation announced today that it has developed a synchronous static random access memory (SRAM) capable of high-speed 500-MHz operation and nearly 100 times more resistant to the cosmic-ray-induced soft errors (1) that plague users of mobile computers during airplane flights.

In addition to meeting the performance requirements of increasingly popular 800-MHz microprocessor units (MPUs), this new technology incorporates a shallow triple-well structure and a stacked memory cell organization (2), both of which provide Mitsubishi Electric's new synchronous SRAM with dramatically improved resistance to cosmic-ray-induced soft errors. Although stacked memory cell organization is commonly used in dynamic random access memory (DRAM) chips, this is the first time it has been successfully employed in an SRAM application. This new SRAM technology is a major contribution to solving the personal computer (PC) industry-wide problem of cosmic-ray-related PC malfunctions, which include data damage and loss.

In recent years, cosmic-ray-induced soft errors in semiconductors have become a major problem for the PC industry. Conventionally, soft errors have originated from the presence of impurities in semiconductor materials and packaging; however, as manufacturing technology has advanced, neutrons from cosmic rays radiating from outer space can be increasingly identified as the major cause of soft errors. In particular, since these neutrons are 100 times more concentrated at passenger flight altitudes (10 kilometers above sea level) than on the Earth's surface, it has become a necessity for semiconductor manufacturers to come up with a solution for jet-setting mobile PC users.

In addition, as the operating frequency of PC MPUs will increase to the 800-MHz level throughout 1999 and into early 2000, the necessity of 500-MHz synchronous SRAM to serve as Level 2 cache memory in PCs is apparent.

Through this new technology, Mitsubishi Electric has been able to create a synchronous SRAM product with the following key characteristics: -0-

--   Dramatically increased resistance to cosmic-ray-induced soft
     errors (several thousand FIT (3) at passenger flight altitudes)
     as well as alpha particle-induced soft errors

-0-

Compared with conventional SRAM, Mitsubishi Electric's new synchronous SRAM is 100 times more resistant to soft errors caused by cosmic rays and 5,000 times more resistant to soft errors originating from alpha particle exposure. Under normal operating conditions, FIT values of up to several thousand is considered sufficient. Mitsubishi Electric's new technology matches this requirement at flight altitudes and reaches 10 or more FIT under normal terrestrial conditions. These improvements are made possible by two architectural advances. First, a new stacked memory cell organization triples the storage node charge of conventional SRAM and consequently has the effect of strengthening resistance to noise "bursts" from neutrons by a factor of 10. This cell organization, commonly used in DRAM, has been realized in an SRAM application here for the first time. Secondly, a shallow triple-well structure, consisting of (from top to bottom) a P-type well, an embedded N-type layer, and a P-type substrate, provides an additional factor of 10 resistance to neutron noise "burst" (for a total factor of 100). This has been accomplished by reducing the thickness of the P-type well, which exerts influence on the capacitor, to one half that of conventional P-type wells. -0-

--   Developed proprietary T-shaped bit line connection (4) that
     achieves an operating speed of 500 MHz

-0-

A proprietary Mitsubishi Electric technology, the T-shaped bit line connection is used to create an improved wiring structure with 20 percent faster operating speeds than can be achieved otherwise. Realizing 500-MHz operation, this connection technology also reduces chip size by 8.5 percent and power consumption by 20 percent.

A more detailed explanation of the technological aspects of the development mentioned above will be given at the International Solid-State Circuits Conference (ISSCC) in San Francisco on February 16, 1999.

Footnote References:

(1) Soft Error -- In contrast to hard errors caused by physical defects in a device, soft errors refer to non-repeating malfunctions that do not originate from hardware problems. In general, soft errors are caused by alpha particles present in semiconductor materials and packaging. These particles create noise burst charges that cause malfunctions. However, soft errors are also caused by neutrons present in the Earth's atmosphere due to cosmic ray activity. The concentration of neutrons from cosmic rays, although low near the Earth's surface, is nearly 100 times more at passenger flight altitudes. Although, during normal usage conditions, Retry and Error Checking and Correction (ECC) functions are available to solve these problems, Mitsubishi Electric's new high frequency SRAM is particularly useful to those who use mobile PCs during airplane flights or at high altitudes.

(2) Stacked memory cell organization -- This structure, a standard organization employed in DRAM since the 4-Mbit generation, consists of a capacitor sandwiched between two layers of polysilicon. Through this structure, it is possible to stack transistors and storage nodes, creating a more concentrated organization. This structure allows for decreased chip size and larger charges in the storage node (which helps avert cosmic-ray-induced soft errors in SRAMs).

(3) Failures In Time (FIT) -- A unit of malfunction occurrence frequency, 1 FIT represents one malfunction every one billion hours (approximately 100,000 years) per device.

(4) T-shaped bit line connection -- This Mitsubishi Electric proprietary technology creates an ideal bit line wiring structure by connecting bit lines in a T-shape. A sense amp is placed on both sides of this array, and it then becomes possible for the data bus to pass through over the array in a structure that reduces chip area size and power consumption while at the same time increases operating speed.

About Mitsubishi Electric and Mitsubishi Electronics America

Mitsubishi Electric Corporation is one of the leaders in providing high-speed and low-power SRAM products in small package sizes, and is known throughout the industry as a market-driven memory supplier to its OEM customer base. Mitsubishi markets its SRAM products in North America through the Electronic Device Group of Mitsubishi Electronics America Inc.

Mitsubishi Electric Corporation and its North American affiliate, Mitsubishi Electronics America Inc., are world-class suppliers of semiconductors and electronic products for computers, communications, industrial and visual applications. Mitsubishi combines its systems-level expertise and high-level silicon process technologies to provide chip, chipset and system-on-chip solutions. The company is ranked among the top-tier worldwide semiconductor suppliers and offers an extensive range of semiconductor and computer system components for the North American marketplace, including embedded DRAM/flash/SRAM, ASIC, ASSP, MCU, discrete memory, graphics, microwave/RF, optoelectronic, storage, and flat-panel display products.

Additional information on the Mitsubishi Electric Semiconductor Group is available at http://www.mitsubishichips.com.