Printer Friendly

Minimizing insertion loss: proper PCB stackup and trace geometry design are key elements in the fight to lower losses.

As bus speeds exceed GHz speeds, signal attenuation due to conductor and dielectric losses absorb a significant portion of the signal integrity budget, especially eye height. Designers need to carefully design their PCB to minimize these losses, while meeting other constraints such as cost, manufacturability and routing density.

For any given impedance (especially differential impedance), an infinite number of trace geometries can be used to attain the impedance target, with a correspondingly infinite number of loss values. A narrow trace can be made less lossy than a wide trace if other parameters (loss tangent, trace thickness, etc.) are not kept constant, even if the impedance is kept constant. In a real-life scenario, however, parameters are going to be bounded, and only certain combinations will be allowed. An exhaustive analysis wasn't practical for this example, nor was a Monte Carlo. Instead, a design of experiments (DOE) (1) approach was used to carefully choose values for sweeps of the variables, which would allow determining each parameter's effect on loss.

Parameter Value Selection

The first step was to identify the parameters that a designer can most easily control: trace type (microstrip or stripline), trace width, trace height, dielectric constant (Er) and loss tangent (DF, dissipation factor). There are other parameters, such as copper conductivity, but those aren't easily changed and their effect is not expected to be significant enough to justify non-standard processing.

A minimum, nominal and maximum range for each parameter that was considered reasonable for standard products was then chosen (TABLE 1).

The rationale for the min and max values are as follows:

* Trace width minimum: smallest dimension currently manufacturable.

* Trace width maximum: largest dimension possible while maintaining reasonable routing densities.

* Trace thicknesses represent typical 0.5 oz., 1 oz. and 1.5 oz (or 0.5 oz. plated) thicknesses.

* The min Er value of 3.4 represents a value for Nelco N4000-13 SI, a readily available (though relatively expensive, compared to FR-4) material. Lower values are available, but only for very expensive materials not likely to be used for high-volume manufacturing.

* The max Er value represents commonly used FR-4.

* The loss tangent values represent those from fairly exotic materials (.007 for Nelco N6000) to commonly used FR-4.

DOE was used to carefully choose combinations of values for the variables that would allow determining each parameter's effect on loss.

Trace Stackup Design

For each combination of variables, a corresponding stackup was designed, one that yielded an impedance of 50 [ohm] for single-ended, or 90 [ohm] for differential. Fifty and 90 [ohm] were chosen as typical values; the results might be different for other impedances, but any differences should be slight.

For the design of the single-ended topologies, some assumptions had to be made. They were:

1. Trace type, width, thickness, Er and DF had to come from DOE.

2. Traces would be rectangular--no trapezoidal "etch factor" would

be included. The etch factor is expected to have minimal effect on the results.

3. Dielectric thickness(es) adjacent to the trace would be adjusted to attain approximately 50 [ohm], as calculated by a 2D field solver (XFX).

4. Microstrip would have soldermask 0.5 mils above the trace, and that soldermask would have the same Er as the dielectric below the trace. These simplifying assumptions may not be completely valid, but shouldn't have any significant effect on the results.

5. Stripline would be symmetrical--the heights of the dielectric above and below the traces would be equal.

6. Stripline would have homogenous dielectric--the same Er surrounding the trace(s).

The single-ended trace topologies are shown in FIGURE 1.


For each stackup, a corresponding Hspice-compatible W-element model was made (using XFX as the field solver and then converting its output to a W-element model).

FIGURE 2 shows the differential topologies, which used the same individual trace geometries as in the single-ended topologies, but with the intra-pair spacing adjusted to attain approximately 90 [ohm] differential impedance. Again, for each stackup a corresponding Hspice-compatible W-element model was made.


Loss Simulation

Once the W-element models were created, they were incorporated into an Hspice deck that would report insertion loss ($21 for single-ended, SDD21 for differential) as a function of frequency for a 5" segment of transmission line. The reference impedance for the differential case was lowered from the standard 50 [ohm] down to 45 [ohm], so that the discontinuity between the simulator reference and the 90 [ohm] differential pair wouldn't cause erroneous loss curves (FIGURE 3).


The resulting families of curves for both the single-ended and differential cases are shown in FIGURES 5 and 6. Notice:


* Careful examination shows that in general, the differential topologies are very slightly less lossy than their single-ended counterparts.

* The boundary cases (least and most lossy) represent extremes of parameters as expected:

* The least lossy is a thick, wide trace, with minimum loss tangent.

* The most lossy is a thin, narrow trace, with a high loss tangent.

* An interesting case (case 0) is a narrow, thin trace, with high loss tangent. It is very lossy at lower frequencies, where its narrow width and thinness make conductor losses maximum, but is less lossy at higher frequencies, where its low dielectric loss tangent plays a larger role.

To be able to assign exact values of loss for each stackup, the insertion loss (for both single-ended and differential cases) at 3 and 6 GHz were extracted. Three and 6 GHz were chosen to represent the frequencies of interest for current busses and those coming in the near future. Most of the curves of Figures 5 and 6 maintain their relative position throughout the frequency span (case 0 is a clear exception), thus conclusions drawn at these frequencies will hold true in general for all the frequencies plotted (20 GHz max). Because there are traces that change relative positions, this is not an absolute, but there shouldn't be dramatic changes if different frequency points were chosen.

The response data (loss value) was then analyzed to evaluate the relative impact of each factor on insertion loss, as shown in Figure 6 (3 GHz) and FIGURE 7 (6 GHz). Note that the lines represent the change in response (loss) due to changes in value of each parameter. For instance, in Figure 6 the upper left box has a strong upward slope, corresponding to more loss when trace width = 3 mils (its minimum), less loss at 5.5 mils (nominal) and the least loss at 8 mils (maximum). The slope of the line indicates how strongly the particular parameter affects the loss for a given set of parameters--shallow slopes indicate very little effect.


Some things of interest to note about FIGURES 7 and 8 (looking at the parameters from left to right):


* Trace width makes a large difference--wide (8 mil) traces are much less lossy than thin (3 mil) traces.

* Trace thickness makes a difference, but not as much as width does.

* Er makes no difference.

* Loss tangent (Df) makes about the same difference as trace width (except that the slope is in the opposite direction--the magnitude is about the same).

* There is very little difference in loss between microstrip and stripline.

It should be highlighted that the strength of the trends is going to be very dependent on the values chosen for the parameters. For instance, width would not be such a strong factor if a range of 3 to 5 mils was chosen instead of 3 to 8 mils. These values do, however, represent best estimates of reasonable ranges for typical PCB designs.

The results showing that microstrip had the same loss as stripline was contrary to conventional wisdom, enough so that an experiment was run to verify those results. With all parameters set to nominal, and dielectric height and spacing adjusted to attain the proper impedances (50 and 90 [ohm] for single-ended and differential, respectively), insertion losses of microstrip and differential traces were plotted. It shows that, except at very high GHz frequencies (where dielectric losses more completely dominate over conductor losses), insertion loss for microstrip and stripline are very similar.

Also, to ensure the results were not prone to errors in the modeler (XFX) or simulator (Hspice), the DOE experiment was repeated using ADS as the field solver and simulator. The results were approximately the same; only XFX[right arrow]Hspice results are reported in the data above.

The previous simulations were done assuming a uniform coating of soldermask, which might have an appreciable effect on the conclusions. An experiment was run in Agilent ADS for microstrip without soldermask, which did reduce the losses for microstrip. However, the effect was not dramatic enough to warrant advocating removing soldermask, which most designs are forced to have.

While there has been much discussion about how much each factor would reduce loss (based on theories, some conflicting), this study conclusively resolves the issue for realistic values of the parameters, constant impedance and today's frequencies.

Designers of future high-speed PCBs will want to use thick, wide traces to minimize insertion loss. If low-loss materials are an option, they will yield great benefit. For loss reduction, neither microstrip nor stripline shows any benefit over the other. There also doesn't appear to be any direct reason to choose a particular Er value. These conclusions may vary a little if different assumptions, geometries or materials are used, but the difference shouldn't be significant. Of course, these conclusions are for insertion loss reduction only--there are many other factors that will influence the final design: crosstalk, routing density, cost, etc.

Armed with this knowledge, designers can more intelligently balance the tradeoffs between impact to loss, cost and manufacturability when deciding exactly what trace type, geometries and materials to use in their stackup.


Special thanks to Richard Kunze and Dave Coleman for their help in editing this article.


(1.) PCI Express Electrical Interconnect Design; Dave Coleman, Scott Gardiner, Mohammad Kolbehdari, Stephen Peters; Intel Press, [c] 2004.

JEFF LOYER is the signal integrity lead engineer for Intel's Enterprise Server Development group. He can be reached at
TABLE 1. Variable ranges considered for each parameter.


Trace Width 3 mils 5 mils 8 mils
Trace Thickness 0.7 mils 1.4 mils 2.1 mils
Er 3.4 3.8 4.2
Loss Tangent (DF) .007 .012 .017
COPYRIGHT 2006 UP Media Group, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion




Article Details
Printer friendly Cite/link Email Feedback
Author:Loyer, Jeff
Publication:Printed Circuit Design & Manufacture
Date:May 1, 2006
Previous Article:Product development for RoHS and WEEE compliance: environmental compliance regs are here to stay. Learn all about them so you can use them to...
Next Article:Imprint patterning: a practical approach to fabrication: this microreplication technique can replace photolithography and laser drilling, with little...

Related Articles
Via modeling for high-speed simulations, Part 1: a method for creating via models and integrating into a network topology for high-speed PCB...
Professional Development Certificate Program.
A designer's survival guide to high-speed serial links: pre-emphasis and backdrilling can help you avoid being a casualty in the battle for signal...
Professional Development Certificate Program.
Technical conference.
Optimizing for 10 Gb/sec differential signal transmission: design fixes that work at 'normal' board speeds can cause havoc in the 10 Gb/sec arena....
Getting your multilayer board fabricated: assumptions can be costly, so communication is more critical than ever.
Designing PCBs with mixed materials: mixing the right high-speed, high-frequency materials can improve your board design and keep costs down. But it...
Effects of plane splits on high-speed signals, Part 2: signal and power integrity degradation can occur in PCBs and IC packages due to high-speed...
Designing for high layer count: the design team plays a major role in reducing emissions, increasing immunity and improving signal quality for...

Terms of use | Copyright © 2014 Farlex, Inc. | Feedback | For webmasters