Microvia-in-pad: possible outcomes and solutions; The features that enable portable technology can cause assembly process predicaments.

When it comes to personal electronics, the smaller and lighter, the better, right? Consumers are willing to pay a premium for devices that lessen the weight they carry on their commute, morning jog or long-distance travel. And once the device is miniaturized to the point it becomes difficult to use--mobile phones, for example--consumers then pay a premium to cram more functionality into the same envelope.

Packing more logic into each semiconductor and using less packaging for the chips achieves this sophistication. The result for electrical designers is devices that have so many inputs and outputs, spaced so tightly, that it is now physically impossible to route the signals in and out of the device on the top layer of the PCB. When this dilemma first arose with the advent of BGAs about 15 years ago, pitches were coarser, and there was enough room to place traditional vias in between the pads, all inside the package footprint. Each I/O was routed to the nearby via, and all the signals were routed through internal layers of the PWB. About 10 years ago, device pitches were shrunk to the level where real estate was too tight to make room for traditional vias. Micro-via-in-pad technology was born. For many years, mainly manufacturers of miniaturized electronics employed microvia technology. In these applications, extended life reliability performance was not a major concern, and most applications used underfill as a standard practice to structurally reinforce the solder joints.

[FIGURE 1 OMITTED]

In the past five years or so, many more devices have emerged requiring the use of microvias in all types of applications, even those demanding long-term reliability. In some cases they are impossible to avoid, as the desired semiconductor chips are only available in packages that require microvia-in-pad technology on the PWB.

Microvias, as indicated by their name, are very small vias, usually less than 0.006" or 150 [micro]m in diameter. They are typically located in the pad center, and can be seen under magnification as small dimples or depressions in the pad. "Under magnification" is the key phrase in this situation. Microvias often can "sneak" into an assembly line without the assembly engineer's knowledge.

Microvias, when they do eventually appear on the assembly line, present several challenges to assemblers. It has been documented that in cases of small discretes like 0402s or 0201s, microvias they can rob solder from the joint being formed, raising reliability concerns. The bigger concern, however, is the issue of voiding when microvias are situated in pads of area array devices such as [micro]mBGAs. The correlation of void size to BGA reliability is a longstanding point of contention in the assembly community.

[FIGURE 2 OMITTED]

Most assemblers avoid the debate, but subscribe to the notion that the smaller and fewer the voids, the better. A print-reflow process that runs typical maximum void size rates in the neighborhood of 5% can see that number soar to 25% and higher when microvias are introduced. Such numbers would alarm any engineer associated with the product under consideration, regardless of their general position on void size and reliability.

Where do these voids come from? In traditional PWB designs without microvias, voids are usually the result of volatiles in the solder paste. Although BGAs can sometimes contain voids in the spheres in their as-received condition, the vast majority of voids in the final assembly are from the assembly process itself. Solder paste by volume is approximately 50% metal and 50% flux. The flux portion is a mixture of many chemicals precisely combined to aid in numerous aspects of stencil printing and soldering. Most of these chemicals are vaporized during reflow. If they are vaporized before the metal portion of the paste deposit melts, it is likely the gasses will escape. Whatever vaporizes after the paste deposit reaches liquidus is likely to remain trapped within the molten metal. Small gas bubbles inside the molten solder are not likely to break the surface tension of the solder to escape, and these trapped gasses are manifested as voids in the final product. While some solder pastes are designated "low voiders" because they outgas quickly enough to provide low levels of voiding on fast ramp reflow profiles, other pastes require soak profiles to permit more complete outgassing before the metal melts and traps those gasses in the joint.

A low voiding paste can repeatedly produce voids of 4% or less as measured by transmission z-ray, so it is safe to assume that up to 5% of total voiding in a solder joint is contributed by the paste. If total voiding in a solder joint is 25%, but only 5% of that can be attributed to solder paste, where did the other 20% come from? From the microvia.

[FIGURE 3 OMITTED]

The depression in the pad, shown at high magnification in Figure 1, traps air during printing. As mentioned, these depressions have diameters of 0.004" to 0.006", or 100 to 150 [micro]m. Type 3 solder powder, which is used in most solder pastes, comes in sphere sizes of 25 to 45 [micro]m. It is highly unlikely that the small depression in the pad will be filled with paste during printing. Even if it were possible to deliver enough print pressure to fill the depressions, the particle packing density would be very low as a result of the relatively large size of the spheres compared with the hole size.

It is impossible to show that the paste is not filling the microvias, because wet prints cannot be cross-sectioned. Reflowed solder joints, however, can be cross-sectioned. Because Pb-free solder does not spread as easily on copper surfaces coated with organic solderability preservative (OSP), but spreads readily on electroless nickel-immersion gold (ENIG) surfaces, comparison of similar joints on both final finishes may provide the necessary evidence of air entrapment. Figures 2 and 3 show 0.5 mm CABGA solder joints on both finishes. Notice the entrapped air, or void, remains in the microvia on the OSP finish. On the ENIG finish, however, solder spreads into the microvia, liberating the void into the bulk of the solder joint.

Many studies have investigated how to limit the contribution of the microvia to void formation, and several methods are now available.

Published Studies

Many studies on microvias and voiding were published in 2003. (1,2,3) To summarize their conclusions, voiding can be mitigated by:

1. Via design. Offsetting the via from the center of the pad, or routing the via completely through the board when space permits. In the first case, the outgassing path is shorter because of the via's offset from the center of the pad. In the second case, the outgassing path is clear, but since gasses like to escape by rising, and in the case of a through-via they must escape through the bottom of the PWB, this is not an optimum condition for limiting voids.

2. Copper-filled microvias, which showed the best results in reducing voiding. Completely filled vias showed less voiding than partially filled vias, presumably because less entrapped air creates less voids.

3. Smaller via sizes, which created smaller voids than larger vias. Again, this is presumably because smaller vias trap smaller volumes of air.

4. Soak profiles, which produced less voids than ramp profiles. These studies were performed prior to the introduction of low voiding paste formulations.

The findings of these studies provided an excellent basis for an investigation that began in 2004 and finished in late 2006. This study examined the effects of:

* Via presence and size.

* Alloy system (SnPb or Pb-free).

* PWB finish.

* Via filling.

The complete report of the study (4) can be downloaded at (http://circuitsassembly.com/cms/content/view/4386/95/). Findings from the study include:

Via presence and size. The test vehicle in the design of experiments (DoE) was designed to compare pads with no vias, 0.004" vias, and 0.006" vias side-by-side on the same assembly. As anticipated, the fewest voids were produced on pads with no vias; more were produced on pads with 0.004" unfilled vias, and the most were produced on pads with unfilled 0.006" vias.

Alloy system. The study used SnPb and SAC305 alloy systems. No mixed metals were investigated. Devices with eutectic SnPb balls were soldered with SnPb solder paste; likewise, devices with SAC305 balls were reflowed with SAC305 solder paste.

For all four device types used in the study, the Pb-free system performed equivalently or slightly better with respect to void production. The performance difference between Pb-free and SnPb was not substantial, but the trend was consistent. This is an important fact to note because, for many years, Pb-free pastes were believed to produce more voids than SnPb. This may have been the case early in the Pb-free transition, when paste formulators were still climbing a steep region of the learning curve. Most formulators now have at least five years of Pb-free experience under their belts, and today's Pb-free pastes often rival the best-in-class characteristics of their SnPb predecessors in every performance category.

[FIGURE 6 OMITTED]

PWB finish. Three surface finishes were included in the study: OSP, ENIG and immersion silver (ImAg). OSP and ImAg generally produced similar amounts of voids, which were less frequent and smaller than those produced with ENIG.

Effect of via filling. The most remarkable result was the effect of filling the vias with copper. The investigators found it impossible to differentiate the voiding performance between filled vias and pads with no vias at all, regardless of device type or alloy.

Figures 4 and 5 show the voiding behavior of 0.8 mm FlexBGA devices. It is easy to visually differentiate the performance of unfilled vias from the other two test conditions. But it is not so easy to discern a performance difference between the pads without vias and the ones for which the vias were filled. The data from these two conditions were analyzed statistically, and it was determined with 95% statistical significance the voiding rates produced on pads with filled microvias are equal to the voiding rates produced on pads with no vias at all.

Figure 6 shows a cross-section of a filled microvia. The via is filled with copper, and the pad surface is nearly planar. There is no room for air to get trapped during printing.

Conclusion

Microvia-in-pad technology is becoming mainstream, and there are plenty of indications that its inclusion can create some relatively large voids in some very small solder joints. The microvias form dimples in pads that trap air during printing, and without a clear outgassing path, the air remains in the solder joint, appearing as a void in the final product.

Removing the dimple in the pad removes the void. Regardless of the area array's device type, ball size, pitch or alloy, and regardless of the pad size, surface finish or via size within the pad, filling the via can completely prevent its contribution to overall voiding rates.

The scientific community continues to disagree regarding the influence of voids on reliability. If it is believed that void inclusion does not affect reliability, then via filling may seem unnecessary. If it is believed that voids do affect reliability, or a maximum allowable void size has been established, filling the vias with copper should be considered. If microvias-in-pad are introduced to product designs as new technologies and a conservative approach to integrating the technology is desired, via filling should definitely be investigated.

Copper via filling can be a proactive, cost-effective solution to the issue of excessive solder joint voiding associated with microvia-in-pad. The best part for the assembler: It is applied during fabrication and requires no added equipment, labor or overhead in the assembly process.

Acknowledgments

The most recent study cited above was a two-year endeavor, and this article is based on the findings of this activity. Many thanks to the many contributors to the study: Rahul Raut and Lou Picchione of Cookson Electronics, Quyen Chu and Nicholas Tokotch of Jabil Circuit, and Dr. Paul Wang of Microsoft.

References

1. F. Grano, et al, "Impact of Microvia in Pad Design on Void Formation," SMTA International Proceedings, September 2003.

2. L. Harjinder, and S. Sundar, "Assembly Issues with Microvia Technologies," SMTA International Proceedings, September 2003.

3. A. Singer, et al, "The Effect of Via-In-Pad Via-Fill on Solder Joint Void Formation," IPCWorks Proceedings, October 2003.

4. C. Shea, et al, "BGA Solder Void Correlation to Via-In-Pad, Via Fill, Surface Finish, and Lead-Free Solder--Final Report," Pan Pacific Microelectronics Symposium Proceedings, January 2007.

Chrys Shea is R & D applications engineering manager at Cookson Electronics Assembly Materials (cooksonelectronics.com); [e-mail]. Dale Lee is principal R & D mechanical engineer at Boston Scientific (bostonscientific.com). Denis Jean is senior staff process engineer at Plexus Corp. (plexus.com).

Ed.: The author will give a workshop on this topic at the Apex Conference later this month.

                     Void Size, % solder joint area
                   1-6  6-11  11-16  16-21  21-26  < 26

No Via             29%  <1%
4mil Via Filled    32%   1%
4mil Via Unfilled  12%   31%  31%    15%    6%     2%

Figure 4. Voiding comparison of pads with no vias, pads with filled
vias, and pads with unfilled vias soldered with SnPb paste.

Note: Table made from bar graph.

                      Void Size, % solder joint area
                   1-6  6-11  11-16  16-21  21-26  26-31

No Via             25%   2%
4mil Via Filled    20%   3%   <1
4mil Via Unfilled  45   23%    6%    2%     <1%

Figure 5. Similar comparison on joint soldered with Pb-free paste.

Note: Table made from bar graph.