Microchip Technology Unveils 16-Bit Digital Signal Controller Architecture.

Business Editors/High-Tech Writers

CHANDLER, Ariz.--(BUSINESS WIRE)--June 6, 2001

dsPIC(TM) Architecture Provides Full-Featured DSP for Free with

Familiar Microcontroller "Look And Feel"

Microchip Technology Inc. (Nasdaq: MCHP) Wednesday unveiled architecture plans for its 16-bit dsPIC(TM) digital signal controllers.

The dsPIC core is a 16-bit (data) non-pipelined modified Harvard RISC machine that combines the control advantages of a high-performance 16-bit microcontroller with the high computation speed of a fully implemented digital signal processor (DSP) to produce a tightly coupled, single-chip single-instruction stream solution for embedded systems designs.

The dsPIC architecture features a full-featured DSP engine, C compiler friendly design, familiar microcontroller-like platform and easy migration of existing code for PIC18 microcontroller users.

With performance of 30 MIPS non-pipelined, the dsPIC architecture provides an ideal solution for many high-performance 16-bit microcontroller and moderate-performance DSP applications such as motor control, soft modems, automotive body computers, speech recognition, echo cancellation, and fingerprint recognition.

The architecture can support up to 4 Mbytes x 24 addressable Flash program memory space and up to 32K x 16 data space. The 2.5-5.5 operating voltage appeals to many microcontroller applications that remain at 5 volts, while many DSPs are restricted to 3.3 supply voltage maximum. Devices are planned in 28-100 pin packages.

The 16-bit microcontroller features 94 instructions and 11 addressing modes. The 16 x 16-bit CPU core working registers can be used as data or address registers, and includes a dedicated register for software stack access. The instruction set comprises a mixture of flexible MCU instructions plus specialized DSP operations that execute from a single instruction stream.

All but a few instructions (including all DSP instructions) execute in a single cycle. Program branches and a few instructions execute in two cycles. The core can complete one or two (for DSP instructions) data memory reads and one data memory write per instruction cycle, using a rich set of addressing modes.

The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance.

A closely coupled DSP engine has been included to significantly enhance the core's arithmetic capability and throughput. It features a high speed 16-bit by 16-bit multiplier, a 40-bit adder, two 40-bit (optionally) saturating accumulators and a 40-bit bi-directional barrel shifter.

Two independent address generation units (AGUs) can concurrently fetch two operands for most of the DSP class of instructions.

A novel dynamically reconfigurable data memory architecture helps maintain a microcontroller "look and feel" by allowing MCU instructions a conventional view of data space while preserving the data memory access bandwidth required by DSP operations.

The CPU core also contains other attributes often found on full-featured DSPs, including bit reversed addressing, zero overhead program looping constructs, and modulo addressing, all of which may be used by any microcontroller application code (i.e. not just DSP-based applications).

In addition, the MCU instructions share other DSP resources such as address generation, multiplier and barrel shifter, increasing performance and code efficiency for many MCU functions.

The dsPIC instruction set architecture was designed from the ground up to be highly efficient for C compilers and RTOSs. The register-based architecture includes a rich set of indirect addressing modes plus many instructions and other features to increase the efficiency of stack operations and task switching. A linear addressing space has been employed without banking.

Furthermore, program space may be transparently accessed through a window in data space, mitigating some of the limitations typical of Harvard DSP architectures.

A flexible vectored exception processing capability supports eight prioritized interrupts and seven traps. Interrupt source priority is user programmable and features fixed latency. Robust device operation in demanding environments is aided through several traps to check CPU operation in addition to an independently clocked watchdog and oscillator failure backup scheme.

With its PICmicro(R) foundation, the dsPIC architecture features many high-performance peripherals typically found on microcontrollers. This includes single-cycle instruction, fault tolerant oscillator, and up to eight capture and eight compare functions for increased pulse-width-modulation flexibility.

For communications capability, the dsPIC family offers combinations of RS-485 type UART, I2C(TM), SPI(TM), AC97, CAN, and I2S for peripheral expansion. A dedicated motor control/power conversion PWM and Quadrature Encoder Interface will also be available. The devices contain up to five 16-bit timers, a watchdog timer, and up to 80 I/O bi-directional ports.

Analog peripherals include 10-bit high speed simultaneous sampling analog-to-digital converters, 12-bit analog-to-digital converters, programmable brownout detect, and programmable low-voltage detect.

Various low power operation modes are available whereby the CPU and peripherals are shut down (though the watchdog timer and real-time clock may run optionally), and alternatively the CPU is shut down but the peripherals continue running. Power can also be managed by PLL control, 32KHz mode and a rapid start internal RC oscillator mode.

The dsPIC digital signal controllers feature In-Circuit Serial Programming(TM) (ICSP(TM)) technology, which allows the devices to be programmed after being placed in a circuit board. This offers tremendous flexibility, reduces development time and manufacturing cycles, and improves time to market.

ICSP also enables reduced cost of field upgrades, system calibration during manufacturing, the addition of unique identification codes to the system and calibration of the system in the field. Requiring only two I/O pins for most devices, Microchip offers the most non-intrusive programming available today.

The dsPIC product family will be employed on Microchip's robust 0.5 micron Flash process technology that provides industry-leading endurance. Microchip plans to meet or exceed all automotive quality and reliability requirements.

Development Tools

Microchip is offering a comprehensive package of development tools and libraries to support the dsPIC architecture. In addition, the company is partnering with many third-party tool manufacturers for additional dsPIC support.

Microchip's MPLAB(R) C30 compiler is a fully compliant ANSI C compiler with standard libraries for the dsPIC architecture. It is highly optimizing and takes advantage of many dsPIC architecture features to provide efficient software code generation. MPLAB C30 also provides extensions that allow for excellent support of the hardware such as interrupts and peripherals.

In addition it is designed to support source-level debugging and is integrated with the MPLAB Integrated Development Environment (IDE). Available at no cost, MPLAB IDE gives users the flexibility to edit, compile, emulate, and program devices all from a single user interface.

Engineers can design and develop code for DSPs in the same design environment they have used for microcontrollers, eliminating the substantial DSP learning curve.

Microchip plans to offer the MPLAB In-Circuit Debugger (ICD) Evaluation Kit to support its dsPIC architecture. MPLAB ICD uses the in-circuit debugging capability of the dsPIC devices and ICSP technology to debug source code in the application, debug hardware in real-time and program a target dsPIC device.

Operating under Microchip's MPLAB IDE, MPLAB ICD offers real-time code execution, in-circuit debugging and built-in programmer.

The dsPIC devices will also be supported by MPLAB ICE, a full-featured full-speed emulator system that offers features not found on traditional DSP emulation environments, such as real-time bus analyzer, hardware breakpoints, and source-level debugging.

High-Volume, Horizontal Applications

Applications that can utilize the advantages of the dsPIC devices include: motor control (sensorless brushless DC, switched reluctance, and induction motors), Internet-connected appliances, automotive products (air bags, body computers, drive by wire, noise reduction, active vibration control), feature telephones (caller ID, echo/noise cancellation, DTMF), digital answering machines (speech compression), low-speed software modems, line card (echo cancellation), POS terminals (encryption, software modem for dial-up), vending machines (software modem, recognition events), biometric security (such as finger print recognition), uninterruptible power supplies, power supply management and natural I/O (speech recognition systems).

Microchip is developing libraries to support many of these applications.

Pricing and Availability

Microchip's dsPIC devices are expected to range from $3-$9 each in 10,000-unit quantities. Beta sampling of the first devices is planned for fourth quarter 2001. General product sampling and hardware development tools are planned for first quarter 2002. Software development tools are expected in August 2001. Volume production is expected in 2002.

The statements contained in this release relating to the expected size of the market for high-volume digital signal controllers, applications for digital signal controllers, package configurations, expected pricing for Microchip's family of digital signal controllers, expected beta sampling dates, and expected start of volume production of Microchip's dsPIC products are forward-looking statements.

These statements involve risks and uncertainties that could cause actual results to differ materially, including but not limited to, future demand for Microchip's products, timely completion and introduction of the dsPIC product line, development of support tools and collateral literature for the dsPIC product line, market acceptance of the dsPIC product line and of Microchip's customers' end-products, competition and competitive pressure on prices and general economic conditions.

Other important risks related to our business are detailed in our Form 10-Q for the quarter ended June 30, 2000 and our Form 10-K for the fiscal year ended March 31, 2000 as filed with the Securities and Exchange Commission.

Microchip Technology Inc. manufactures the popular PICmicro(R) field-programmable RISC microcontrollers, which serve 8- and 16-bit embedded control applications, and a broad spectrum of high-performance linear and mixed-signal, power management and thermal management devices.

The company also offers complementary microperipheral products including interface devices; microID(TM) RFID devices; serial EEPROMs; and the patented KEELOQ(R) security devices. This synergistic product portfolio targets thousands of applications and a growing demand for high-performance designs in the automotive, communications, computing, consumer and industrial control markets.

The company's quality systems are ISO 9001 (1994 version) and QS9000 (1998 version) certified. Microchip is headquartered in Chandler, with design facilities in Mountain View, Calif. and Bangalore, India; semiconductor fabrication facilities in Tempe and Chandler, Ariz. and Puyallup, Wash.; and assembly and test operations near Bangkok, Thailand.

Microchip employs approximately 3,050 people worldwide and has sales offices throughout Asia, Europe, Japan and the Americas. More information on the company can be found at www.microchip.com.

Note: The Microchip name and logo, PIC, PICmicro, MPLAB and KEELOQ are registered trademarks of Microchip Technology Inc. in the United States and other countries. dsPIC is a trademark of Microchip Technology Inc. in the United States and other countries. I2C is a trademark of Philips Corp. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.