Micro Memory Unveils the CoSine System-on-Chip for Real Time FPGA-based Signal Processing.

CHATSWORTH, Calif. -- Micro Memory(R), LLC:

--CoSine(TM) is a fully integrated, preconfigured SoC that bridges two high-speed interfaces (Serial RapidIO(R), PCI-X, or PCI-Express) through a multi-port DDR controller, enabling non-contentious access to a User Programmable Logic block.

Micro Memory(R), LLC (www.micromemory.com) today announced CoSine, a highly-integrated, completely preconfigured System-on-Chip for real-time FPGA-based signal processing. Bridging two high-speed interfaces (Serial RapidIO(R), PCI-X(TM), or PCI-Express(TM)) through a multi-port DDR controller, the elegant design enables non-contentious access to a User Programmable Logic (UPL) block and QDR II SRAM controller.

"CoSine is a truly impressive System-on-Chip," said Erich Goetting, Xilinx Vice President & General Manager, Advanced Products Division. "By combining Micro Memory's high-performance custom logic with multiple PowerPC(R) cores, Multi-Gigabit Rocket I/O(TM) Transceivers, and Xilinx(R) LogiCORE IP(TM), CoSine represents an excellent example of what can be achieved with the Virtex-II Pro(TM) family of FPGA's. As the cornerstone of Micro Memory's embedded platforms, this IC should prove a key enabler for next-generation signal processing equipment."

Similar to a structured ASIC, the IP cores, memory controllers, specialized DMA engines, embedded processors and surrounding logic are factory preconfigured and supplied as a fully tested system. This provides users the ability to focus on application specific state machine processing

in the UPL block without concerning themselves with coding other modules, complicated SoC integration, or verification.

CoSine not only combines the functionality of several chips into a single device, but, with a focus towards processing real time data streams, CoSine's elegant architecture enables data to flow through different internal FPGA elements with non-contentious access.

Signal processors spend a significant portion of time and resources moving data, shuffling it in preparation for manipulation. "Through the use of a large, multi-ported memory buffer tightly integrated with the UPL block and a corner turning DMA engine, CoSine significantly reduces this inefficiency for downstream DSP's," said Mike Jadon, Director of Product Marketing, Micro Memory. "This unique combination enables downstream DSP's to spend a higher percentage of time and resources on intelligent data manipulation, reducing overhead and system complexity."

While targeting streaming signal sensor applications such as synthetic aperture and phased array radar, software defined radio, signal intelligence, and semiconductor and medical imaging, CoSine also addresses the requirements of enterprise network storage for file system and data compression.

FPGA-based digital signal processing is particularly relevant to all of these applications because it provides the ability to perform multiple functions in parallel that would otherwise be executed in a serial mode on a conventional DSP or embedded processor (Altivec(R) PowerPC, TI(R) C6x(TM), etc). Algorithms for fixed point functions such as FFT's, FIR, data convolution, reduction and digital down conversion are often well-suited to take advantage of internal FPGA resources such as multiply/accumulators, RAM, FIFO's and look up tables.

CoSine's architecture and internal connectivity are logically optimized for input data to flow through pipelined, parallelized operations in the UPL block, with results DMA'd to conventional downstream DSP compute nodes for intelligent processing.

By offloading computationally intensive functions from conventional DSP's, CoSine can increase overall system performance while reducing total board count, total power consumption, system cost and complexity.

The CoSine development toolkit includes a standalone ATCA(R) board with up to 8GB of DDR that demonstrates continuous sustained transfers from a 64-bit/133MHz PCI-X PrPMC site at maximum bandwidth through CoSine to a Serial RapidIO x4 XMC site. Along with a complete "How to" Developer's Manual, the kit includes a demo program using an off-the-shelf Xilinx 1024 FFT, a robust library of VHDL test benches, and an extensive suite of PCI, Serial RapidIO, and standalone diagnostic "C" test code.

In addition to the ATCA form-factor of the development board, CoSine will be offered on several forthcoming XMC, AMC, and Othello VME VxS VITA 41 and 46/48 formats.

Micro Memory, LLC, is a leading provider of board-level products for streaming signal and image processing, real-time data acquisition, and enterprise network storage. Headquartered in Chatsworth, Calif., the company's innovative products solve challenging problems for industry-leading OEM's and system-solution providers. For information: www.micromemory.com.