Mentor Graphics and MIPS Technologies Unveil Complete Solution for Pre- to Post-Silicon SoC Development.

Business Editors, High Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 8, 2000

Addressing the growing needs of System-on-Chip (SoC) designers, Mentor Graphics Corporation in cooperation with MIPS Technologies, Inc. (NASDAQ: MIPS), today unveiled a complete integrated environment for pre- to post-silicon development. The end-to-end development and debug solution provides SoC designers with a single graphical user interface based on the Mentor Graphics(R) XRAY(R) Debugger. The integrated environment rapidly accelerates time-to-market for complex SoC designs incorporating MIPS Technologies' 32-bit processor cores in popular networking, communications, digital consumer and portable applications. Evaluation systems that encompass both cores and development tools are now available for MIPS Technologies' licensees and their customers.

With market demands forcing shortened design schedules, new systems must be developed, tested and deployed rapidly, while still maintaining low overall system cost. To ease this time-to-market pressure, developers require the ability to rapidly perform multi-core debug, hardware/software co-verification, and hardware acceleration followed by on-chip and synchronized software debugging in a unified flow. Mentor is the first to provide an integrated pre-to-post silicon environment that addresses the requirements of SoC design.

&uot;Mentor Graphics understands the issues faced by our mutual customers involved in System-on-Chip design,&uot; said Brian Knowles, vice president of marketing for MIPS Technologies, Inc. &uot;From industry standard co-verification tools to post-silicon debugging, Mentor is the first and only company to offer a comprehensive, integrated environment for the end-to-end development and debug of SoCs. As the popularity of standard core designs based on the MIPS32 and MIPS64 architectures continue to increase, this solution will make it easier for MIPS-based developers to incorporate our processor cores into their high-performance SoC designs.&uot;

The Pre-Silicon Stage

Throughout each stage of the SoC design cycle, the Mentor Graphics XRAY Debugger serves as the cockpit for managing all phases of development. Before hardware is available or the hardware design is complete, XRAY can be used with the MIPS32 Instruction Set Model (ISM) to enable testing and prototyping of the application software. XRAY enables applications to be exercised on a host-resident model of the target processor core, making it the ideal pre-hardware tool because it works with the same source code and build environment that will be used with the actual hardware.

Once the hardware design is underway, XRAY works in combination with the Mentor Graphics Seamless(R) Co-Verification Environment (CVE) to verify the hardware/software integration all the way to fabrication, reducing or eliminating the possibility that errors will remain undiscovered in the final silicon. This process helps ensure first pass success.

The Post-Silicon Stage

For software debugging on either prototype or final hardware, XRAY supports host-target connection via the eJTAG (Enhanced JTAG) interface.

XRAY OCD(TM) uses the Raven(TM) eJTAG interface from Macraigor Systems Inc. to provide non-intrusive hardware-assist debugging of real hardware. Unlike target-resident monitor connections, on-chip debugging (OCD) is the ideal solution for resource-constrained SoC designs since it does not require any target resources, such as memory and dedicated communication channels, for debugging.

&uot;Mentor Graphics is driving an important standardization effort for MIPS-based designs in high-growth areas such as telecommunications and consumer electronics,&uot; said Michael Kaskowitz, vice president and general manager of the Embedded Software Division of Mentor Graphics. &uot;We have worked closely with MIPS Technologies to define a complete platform using existing best-in-class tools for pre- to post silicon development.&uot;

Availability

The Mentor Graphics development tools for the MIPS32 family of processor cores are now available on a wide range of hosts and targets including Sun Solaris and Windows98/NT. Contact your local Mentor Graphics sales representative or visit our web site at http://www.mentor.com/embedded for the latest information about availability for specific hosts, target and execution environment combinations.

About the XRAY Debugger

The XRAY Debugger for MIPS32 expands on the Mentor Graphics strategy to provide advanced debug capabilities for SoC designs. To support the whole SoC development team, the XRAY Debugger product line includes versions that support instruction-set simulation and co-verification, as well as hardware-assisted debugging of evaluation and prototype hardware. XRAY provides a common interface to the complete set of tools for debugging embedded applications, which improves developer productivity and eliminates the need to learn multiple user interfaces.

For more information please visit http://www.mentor.com/embedded, or call 800/ 950-5554 or 408/ 487-7000.

About Seamless CVE

Linking the best in embedded software development tools with logic simulation, Mentor Graphics Seamless CVE is the market leader in hardware/software co-verification with a 62% market share as reported by Dataquest. Seamless CVE delivers high performance co-verification months before a hardware prototype can be built, allowing software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

About MIPS Technologies, Inc.

MIPS Technologies, Inc. is one of the world's primary architects of embedded 32- and 64-bit RISC processors. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers, and system OEMs. MIPS Technologies, Inc. and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products.

Licensees currently include: Alchemy Microprocessor Design Group (Cadence); ATI Technologies Inc.; Broadcom Corporation; Centillium Communications, Inc.; Chartered Semiconductor Manufacturing Ltd.; CommQuest (IBM); ESS Technology, Inc.; Excess Bandwidth Corporation; General Instrument Corporation; Integrated Device Technology, Inc. (IDT); Lara Technology, Inc.; LSI Logic Corporation; Macronix; Metalink Ltd.; NEC Corporation; NKK Corporation; Philips Semiconductors; Quantum Effect Devices, Inc. (QED); Sandcraft, Inc.; SiByte, Inc.; Sony Corporation; Synova; Texas Instruments Incorporated; and Toshiba Corporation. Numerous companies utilize MIPS-based intellectual property. MIPS Technologies, Inc. is based in Mountain View, California, and can be reached at 650-567-5000 or http://www.mips.com.

About Mentor Graphics Corporation

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of $500 million and employs approximately 2,600 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

NOTE TO EDITORS: Mentor Graphics, Seamless and XRAY are registered trademark of Mentor Graphics Corp. Co-Verification Environment and CVE are trademarks of Mentor Graphics Corp. All other company or product names are the registered trademarks or trademarks of their respective owners.