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Mentor Graphics Verifies Clock-Domain Crossing Solution for Sun Microsystems UltraSPARC T1 Processor.


WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corporation (Nasdaq:MENT) today announced its 0-In(R) Clock-Domain Crossing (CDC See Control Data, century date change and Back Orifice.

CDC - Control Data Corporation
) technology was used in the design of Sun Microsystems' breakthrough UltraSPARC(R) T1(TM) processor, which Sun recently announced. The UltraSPARC T1 processor with patented CoolThreads technology is an eight-core 64-bit, 32-thread processor design which includes open-source hardware and software specifications.

Mentor Graphics(R) 0-In CDC technology was critical to Sun's overall verification methodology. The processor design maximizes performance and lowers power consumption through an innovative multi-clock architecture in which relatively slow cores share an onboard memory controller and I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 subsystem through a high speed crossbar switch An earlier telephone switch. First used in the late 1930s, it was a mechanical device that used magnets and metal bars (crossbars) to close connections. Crossbar switches have been replaced with electronic switches (large-scale, specialized computer systems). See ESS and DMS. . The result is high throughput with low memory latency In computing, memory latency is the time between initiating a request for a byte or word in memory until it is retrieved. If the data is not in the processor's cache, it takes longer to obtain them, as the processor will have to communicate with the external memory cells.  and low power. Sun selected the 0-In CDC technology because of its unique ability to thoroughly check ratioed synchronous clocks and lock-up latches as well as asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end.  clocks.

Sun looked at a variety of options to address metastability met·a·sta·ble  
adj.
Of, relating to, or being an unstable and transient but relatively long-lived state of a chemical or physical system, as of a supersaturated solution or an excited atom.
 and other CDC-related issues and decided to use formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 techniques. After evaluating available technologies, they selected the Mentor Graphics 0-In CDC solution. Close collaboration between Mentor and Sun ensured that the design was free of CDC problems and reached verification closure on schedule.

"We had two or three months to formally verify the crossings," stated Eugena Talvola, senior verification engineer for the Formal Technologies Group at Sun. "Adding to the pressure was the fact that CDC verification was a new area for us. We needed certain features that nobody had. The 0-In CDC product implemented checking for ratioed synchronous clocks and lock-up latches for us. The Mentor team worked with our R&D staff to implement it on a fairly short notice, in time to check the chip."

The UltraSPARC T1 processor had a few hundred ratioed synchronous clocks -- synchronous clocks with different frequencies. Ratioed synchronous clocks allow the cores to be much more portable because the memory controller and the I/O subsystem can be quickly modified to meet new requirements or standards without changing the core.

The 0-In CDC tool checked lock-up latches used for production testing. Lock-up latches were inserted to delay certain branches of the clock tree by half a cycle. Clock domains can be defined by the user, so clock A and clock B may be branches of the same clock tree if necessary. This is usually used to make sure that a scan chain Scan chains are a technique used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. A special signal called scan enable is added to a design.  does not pass through more than one bit per shift cycle due to clock skew In circuit design
In circuit design, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.
. Because the 0-In CDC tool could detect where the clock domain crossings were, it was able to check whether the lock-up latches were in place.

"Sun and Mentor's 0-In team have had a solid working relationship and we are proud of being a vital contributor to the UltraSPARC T1 processor," said Steve White, general manager of Mentor Graphics 0-In functional verification business unit. "We foresee further collaborations with Sun and its OpenSPARC initiative as they continue to deliver innovative open-source multi-threading technologies to the industry."

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County.  95131-2314. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and 0-In are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
COPYRIGHT 2006 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Apr 25, 2006
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