Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa.WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corporation (Nasdaq:MENT) today announced the Questa(TM) Vanguard Program (QVP QVP Quality Vendor Program QVP Quad Voice Processor (Ditech Communication) QVP Quality Verification Plan QVP Quick View Plus ), a partnership with industry-leading companies to enhance the verification options for Questa users and build a strong and comprehensive SystemVerilog ecosystem. The Questa Vanguard Program extends Mentor Graphics breadth of verification technologies through partnerships with other industry-leading companies that provide verification-related tools and methods, verification IP, conversion services, training and consulting. Through these technology alliances and strategic partnerships, Mentor Graphics leverages resources and technical expertise to deliver even greater value to Questa users, including strong product integration with other Mentor Graphics technologies (see news release "Mentor Graphics Delivers the Next Generation of Functional Verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, ," May 8, 2006). "Without adequate industry infrastructure, no new technologies or methodologies can be successful," said Dennis Brophy, director of strategic business development at Mentor Graphics. "Mentor Graphics is committed to work closely with partners to ensure full support of the Questa platform." With the Questa Vanguard Program, Mentor has joined forces with leaders (see list of vendors enclosed) in training, consulting, conversion services and verification intellectual property (IP) to simplify and accelerate the adoption of new verification languages and techniques. Each partner works closely with Mentor to ensure that their products support the Questa platform and the Advanced Verification Methodology (AVM AVM 1 Acute viral meningitis, see there 2 Arteriovenous malformation, see there ). In particular, Mentor has worked with select partners to facilitate the availability of their conversion products and services to help users rapidly migrate from proprietary single-vendor languages to SystemVerilog and the AVM. QVP enables design and verification engineers to meet today's verification challenges by extending and augmenting the Questa solution via Mentor's partnerships, thus allowing customers to identify the right partner for their verification needs. With a strong balance of QVP partners that support a broad set of verification IP, Mentor Graphics leverages the verification IP qualified for use with the Questa platform to deliver greater value to Mentor customers. QVP partners support more than 30 protocols with over 50 verification IP elements. Membership in the Questa Vanguard Program is open to those companies who work with Mentor Graphics verification customers and wish to promote the development and use of EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools, verification IP, training services and verification methodology consulting that support the SystemVerilog standard for design and verification. QVP members gain access to the Questa platform to ensure design and verification data interoperability and to provide support for mutual customers. In addition, Questa has been designed to work with Mentor's ModelSim(R) partner tool integrations, design libraries, and others services, which represent more than 500 products and services from over 100 companies. For information on how to join the program, visit www.mentor.com/questa or send an email to qvp_program@mentor.com. Questa Vanguard Program Partner Statements Averant Inc. "We are pleased to be part of Mentor's Questa Vanguard Program. This collaboration is a very effective step toward providing customers with powerful and tightly integrated design The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. and verification flows." Dr. Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo. Hojati, president of Averant, Inc. Doulos Ltd. "Doulos has partnered with Mentor for the benefit of our mutual customers over many years, and we are pleased to be engaged further in the Vanguard initiative. Embedding 1. (mathematics) embedding - One instance of some mathematical object contained with in another instance, e.g. a group which is a subgroup. 2. (theory) embedding - (domain theory) A complete partial order F in [X -> Y] is an embedding if the 'know-how' necessary for effective verification within our customer base is what Doulos excels at; Vanguard will enable us to do that more effectively for Questa users." Rob Hurley, Managing Director, Doulos Denali Software Denali Software, Inc. is an American software company, based in Palo Alto, California. The company produces electronic design automation (EDA) software and intellectual property (IP) design cores for memory and other standard interfaces. , Inc. "Mentor Graphics is demonstrating its leadership in SystemVerilog solutions with Questa. Using Questa's native implementation of SystemVerilog, we were able to deploy a very sophisticated coverage-driven, constrained-random verification environment that fully utilized the advanced features of Denali's verification IP products. This is key to enabling shorter development cycles, and higher-quality results. Questa takes full advantage of SystemVerilog by providing a single kernel verification solution that offers significant performance and debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. advantages over the previous generation of multi-tool, multi-language solutions." Brian Gardner Brian Gardner is an American record producer and sound engineer. He has worked on over 750 recordings since the mid-1970s, including classic rock, funk, disco, alternative rock, R&B, hip hop, pop punk, and dance pop. , vice president of IP products at Denali eInfoChips Ltd "Questa provides an integrated development environment See IDE. integrated development environment - interactive development environment , which enables engineers to work with assertions, coverage and edit code, view waveforms all in a single window, resulting in reduced time-to-debug." Nilesh Ranpura, Sr. Engineering Manager at eInfochips Europe Technologies SA "Europe-Technologies (ET) decided to use Questa and SystemVerilog for all the IP verification. Questa responded to ET's needs: using Mentor Graphic's AVM (Advanced Verification Methodology), ET was able to develop new verification libraries by exploiting the powerful new standard SystemVerilog language." Dennis Ramaekers, Europe Technologies Expert I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output "ExpertIO, the industry leader in Verification IP for multi-gigabit storage and networking protocols, fully supports the Questa tool platform. As a supplier of natively compiled Verilog/SystemVerilog SVCs (System Verification Components), our solutions offer the most performance from Questa for more verification cycles. For more information about ExpertIO's SATA (Serial ATA) A serial version of the ATA (IDE) interface, which has been the de facto standard hard disk interface for desktop PCs for more than two decades. The original Parallel ATA (PATA) interface was launched in 1986. , SAS (1) (SAS Institute Inc., Cary, NC, www.sas.com) A software company that specializes in data warehousing and decision support software based on the SAS System. Founded in 1976, SAS is one of the world's largest privately held software companies. See SAS System. , FiberChannel, and XAUI XAUI 10 Gigabit Attachment Unit Interface XAUI Extended Auxiliary Unit Interface XAUI XSBI Attachment Unit Interface (IEEE 802.3ae) XAUI Ten Gbps Attachment Unit Interface SVCs, please visit www.expertio.com." Craig Stoops, President -- ExpertIO, Inc. HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. Design House "HDL Design House joined the Questa Vanguard Program a year ago. We saw a tremendous boost in our SystemVerilog-based Verification IP product quality. The development cycle for our Verification IP shortened beyond our expectation. Our prospects and customers responded positively to our newly introduced SystemVerilog VIP, which is compliant to the AVM. The Mentor Graphics QVP team fully understood and addressed our needs accurately, enabling us to accelerate our implementation schedule for our products." Bogdan Bizic, SV Verification Product Manager, HDL Design House hd Lab, Inc. "hd Lab is honored to be a member of the Questa Vanguard Program. We are able to provide to all Japanese design and verification engineers comprehensive SystemVerilog training classes based on the Questa as a best in class SystemVerilog & SystemC verification environment." Mr. Hasagawa, Founder and President of hd Lab nSys Design Systems Pvt. Ltd "SystemVerilog is a very important standard for system-level verification and gaining wide acceptance rapidly as users have an alternative to proprietary languages or solutions. nSys is committed to support its nVS family of Verification IP on SystemVerilog and we appreciate Mentor's effort to support SystemVerilog by providing a complete standards-based verification environment with Questa." Atul Bhatia, Director of nSys, Inc. Paradigm Works, Inc. "Paradigm Works is engaged with helping a growing number of companies that are in the process of adopting SystemVerilog as the language of choice for designing and verifying complex ASICS ASICS Anima Sana in Corpore Sano (Japanese shoe manufacturer; Latin: a sound mind in a sound body) , FPGAs, Design IP, and Verification IP. For the long-term success of these projects, vendor support for the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1800-2005 standard and the adoption of advanced verification and design methodologies are critical requirements. We believe that with the release of Questa 6.2, and its support for AVM and TLM TLM Telemetry TLM Transaction Level Modeling TLM Tout Le Monde (French) TLM The Leprosy Mission (Northern Ireland) TLM Transmission Line Matrix TLM The Little Mermaid (fairy tale) methodologies, Mentor has taken these requirements very seriously." Dr. Ambar Sarkar Sarkar could mean:
Real Intent, Inc. "As the leading supplier of Formal Analysis solutions, Real Intent is very pleased to work with the Questa team. Mentor is to be praised for rapid adoption of System Verilog and we are ensuring compatibility between Verix and Questa. Our Clock Intent Verification -- SimPortal application directly leverages Questa, and we are actively working to deliver superior solutions to our joint customers." Prakash Narain, President & CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. , Real Intent SpiraTech Ltd. "The QVP program is as innovative as the product it seeks to enhance. Mentor has been very proactive in engaging its partners and provides an unusually high level of support to third-party vendors during the integration phase. Mentor has a very clear and complete vision of what a System Level DVT See deep vein thrombosis. platform should be and with Questa, QVP and AVM have gone a long way to delivering it. SpiraTech shares their vision and will ensure that our Transactors, BFMs and other Verification IP embrace the Advanced Verification Methodology and that they are seamlessly integrated with Questa." Simon M. Calder, CEO SpiraTech Ltd Sunburst Design Inc. "Sunburst Design, long-time provider of world-class SystemVerilog seminars and training using ModelSim and Questasim, looks forward to using Mentor's Questasim 6.2 simulator with enhanced SystemVerilog support in its advanced training classes. Sunburst Design recognizes that life is too short for bad or boring training, and the latest release of Questasim will allow us to offer even greater lab experiences for engineers looking to adopt SystemVerilog design and verification skills and methodologies from training materials developed by renowned Verilog & SystemVerilog expert, Cliff Cummings. Sunburst Design also congratulates Mentor for releasing a freely downloadable Advanced Verification Methodology manual with coded examples to assist engineers in the implementation of new and advanced SystemVerilog verification environments." Cliff Cummings -- President, Sunburst Design, Inc. World Class Verilog & SystemVerilog Training www.sunburst-design.com Sutherland HDL, Inc. "Sutherland HDL, a leader in advanced SystemVerilog training, has been pleased to use Questa in our training workshops, and to be an evaluator of Questa 6.2 and AVM. Questa provides our students with the capabilities needed as they learn to take full advantage of power of SystemVerilog for design and verification. The Questa graphical user interface graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to is easy to learn and provides the insight needed to understand and use SystemVerilog assertions, coverage, and constrained random test generation." Stuart Sutherland Norman Stuart Sutherland (26 March 1927 - 8 November 1998), always known professionally as Stuart Sutherland, was a British psychologist and writer. Sutherland was educated at King Edward's School, Birmingham before going to Magdalen College, Oxford, where he read , President, Sutherland HDL, Inc. VeriEZ Solutions, Inc. "VeriEZ is strongly committed to supporting technologies that enable wide-spread adoption of the SystemVerilog language. The Advanced Verification Methodology (AVM) is sure to add tremendous value to verification flows, and we would like to commend Mentor for such a timely offering. As a member of the Questa Vanguard Program, we look forward to integrating VeriEZ's SystemVerilog solutions with AVM." Sashi Obilisetty, President & CEO, VeriEZ Vericine Ltd. "Vericine is very happy to join Questa Vanguard Program. As in the past Mentor Graphics has proved to be very helpful. Vericine provides best-in-class verification solutions for its customers and working with Mentor's pure SystemVerilog solutions helps us to achieve this goal." Ronen Hadar, Principal Consultant & General Manager, Vericine Verilab, Inc. "The Questa Vanguard Program brings together powerful verification tool and platform technologies, an effective verification methodology, and a network of expert consulting partners that will help lift verification teams to higher degrees of effectiveness. Questa itself is a practical and powerful integrated solution for developing state-of-the-art verification environments utilizing both SystemVerilog Assertions and SystemVerilog Testbench language constructs. Questa 6.2 in particular promises to bring language support, capability and simulation performance to even higher levels. The Mentor AVM in turn represents a significant open-source contribution to the verification community. It enables effective and efficient SystemVerilog and SystemC verification environments to be developed by engineers with different levels of expertise, through clear documentation and executable example code presented in a lightweight and practical cookbook (programming) cookbook - (From amateur electronics and radio) A book of small code segments that the reader can use to do various magic things in programs. One current example is the "PostScript Language Tutorial and Cookbook" by Adobe Systems, Inc (Addison-Wesley, ISBN format." Mark Litterick, Co-Founder, Verilab XtremeEDA Corporation "SystemVerilog, as an open standard HVL HVL, n See half-value layer. HVL half-value layer. , is an ideal language to develop modern coverage-driven, constrained-random assertion-based verification environments. Mentor's Questa 6.2 simulator implements all of the key features of the language and enables verification engineers to achieve the full potential of the standard. We are pleased to be a partner in the Questa Vanguard Program." Dr. Paul Marriott, Director of Verification, XtremeEDA Corporation Willamette HDL, Inc "We've been working with Mentor Graphics for the last several months to train its customers and applications engineers on the Advanced Verification Methodology using the new release of Questa. We've helped debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. the software by providing a communications channel Also called a "circuit" or "line," it is a pathway over which data are transferred between remote devices. It may refer to the entire physical medium, such as a telephone line, optical fiber, coaxial cable or twisted wire pair, or, it may refer to one of several carrier frequencies for its customers to offer feedback. As verification training specialists, we've been impressed with this new version of Questa and wholeheartedly whole·heart·ed adj. Marked by unconditional commitment, unstinting devotion, or unreserved enthusiasm: wholehearted approval. whole support Mentor Graphics' efforts to further SystemVerilog adoption and this verification methodology." Mike Baird, President, Willamette HDL, Portland, Ore. www.whdl.com About Mentor Graphics Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services Noun 1. consulting service - service provided by a professional advisor (e.g., a lawyer or doctor or CPA etc.) service - work done by one person or group that benefits another; "budget separately for goods and services" and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon Wilsonville is a city in Clackamas County, Oregon, United States. The population was 13,991 at the 2000 census, and as of 2005 was estimated to be 16,510.[1] Geography Wilsonville is located at (45.306805, -122. 97070-7777. World Wide Web site: http://www.mentor.com/. Mentor Graphics and ModelSim are registered trademarks and Questa is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners. Questa(TM) Vanguard Program (QVP) Members 1. Ace Verification Corp. 2. ARM, Ltd. 3. Averant Inc. 4. Doulos Ltd. 5. Denali Software, Inc. 6. eInfoChips Ltd 7. Europe Technologies SA 8. Expert I/O 9. HDL Design House 10. hd Lab, Inc. 11. MU Electronics SARL SARL South African Radio League SARL Société Anonyme à Responsabilité Limitée (French: limited liability company) SARL Salem Animal Rescue League (Salem, NH) SARL Sociedade Anónima de Responsabilidade Limitada 12. NoBug Inc. 13. nSys Design Systems Pvt. Ltd 14. PSI Electronics SARL 15. Paradigm Works, Inc. 16. Real Intent, Inc. 17. SiManits Inc. 18. SpiraTech Ltd. 19. Summit Design 20. Sunburst Design Inc. 21. Sutherland HDL, Inc. 22. SyoSil 23. VeriEZ Solutions, Inc. 24. Vericine Ltd. 25. Verilab, Inc. 26. Vhdl Cohen cohen or kohen (Hebrew: “priest”) Jewish priest descended from Zadok (a descendant of Aaron), priest at the First Temple of Jerusalem. The biblical priesthood was hereditary and male. Publishing 27. Willamette HDL, Inc 28. XtremeEDA Corporation |
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