Printer Friendly
The Free Library
14,581,301 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

Mentor Graphics Extends Catapult C Synthesis Product; Enables 20X to 100X Faster Verification with SystemC.


WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corporation (Nasdaq:MENT) today announced extensions to its Catapult(TM) C Synthesis algorithmic synthesis tool, a leading electronic system level (ESL (1) An earlier family of client/server development tools for Windows and OS/2 from Ardent Software (formerly VMARK). It was originally developed by Easel Corporation, which was acquired by VMARK. ) design tool. These extensions enable the Catapult C Synthesis tool to automatically create SystemC transaction-level models and wrappers In data mining and treatment learning, wrappers were used by Ron Kohavi and George John. Their idea was to wrap their treatments learners in a preprocessor that would search to make subsets from the current set of attributes. , allowing designers to rapidly explore architectural tradeoffs and simulate their designs 20X to 100X faster than traditional register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) using verification environments that support SystemC, like Mentor's ModelSim.

"The combination of algorithmic synthesis from pure ANSI C (language, standard) ANSI C - (American National Standards Institute C) A revision of C, adding function prototypes, structure passing, structure assignment and standardised library functions. ANSI X3.159-1989.

cgram is a grammar for ANSI C, written in Scheme.
++ with an integrated SystemC verification environment provides a powerful solution for ESL design," said Simon Bloch, general manager of the Mentor Graphics Design Creation and Synthesis Division. "For the first time, designers now have a methodology for easily implementing a 'golden source' from the algorithmic level of abstraction The level of complexity by which a system is viewed. The higher the level, the less detail. The lower the level, the more detail. The highest level of abstraction is the single system itself.  down to technology-specific RTL. With the ability to generate SystemC models, designers can now rapidly explore architectural tradeoffs and verify their design, while re-using existing C++ and SystemC testbenches throughout the flow."

Venkat Rangan, senior staff engineer for QUALCOMM, commented on the Catapult C Synthesis verification extension, "The new enhancements to Catapult C promise to automate the time-consuming process of SystemC model creation. Automatic SystemC model generation has great potential to accelerate block- and system-level verification, which would enable designers to produce better hardware much faster than before."

Traditionally, designers had to manually re-write their C algorithms into SystemC, a slow and painstaking process of incremental refinement, adding the structure, parallelism, and interfaces necessary for SystemC. Instead of this manual progressive refinement Progressive Refinement is a ray tracing algorithm that quickly reveals coarse structure of an image, and gradually reveals additional detail over time.

The first pixel is rendered as a single rectangle occupying the entire work area.
, the Catapult C Synthesis tool now automatically adds these hardware details to the algorithmic C++ model to generate a cycle- and bit-accurate behavioral SystemC model.

Hardware designers can then employ Mentor's scalable verification platform to rapidly verify generated models. The interface of the SystemC model has the same behavior as the RTL generated by Catapult C Synthesis, but is optimized to simulate 20-100X faster. Designers can, therefore, more rapidly explore and verify architectural tradeoffs and achieve faster verification of their optimized designs.

The Catapult C Synthesis tool enables designers to use algorithmic C++ models as a "golden source." The tool employs interface synthesis and sequential-to-structural transformations to automatically generate SystemC or RTL hardware descriptions without changing the original sequential C++ source. Currently, Catapult C Synthesis uses C++ to produce behavioral SystemC models that simulate 20-100X faster than RTL, with future releases intended to generate more abstract transaction-level SystemC models that simulate more than 1000x faster than RTL.

The tool's interface synthesis technology also helps generate transactors that synchronize timed RTL with a sequential or transactional test environment. This connection allows designers to use a single sequential C++ or SystemC-based testing environment for the entire design flow. Catapult C Synthesis can also generate a testbench that automatically compares the C++ input to the RTL output, providing debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits.  information for specific synchronization (1) See synchronous and synchronous transmission.

(2) Ensuring that two sets of data are always the same. See data synchronization.

(3) Keeping time-of-day clocks in two devices set to the same time. See NTP.
 points in the case of a simulation mismatch. These capabilities allow designers to use or re-use sequential C++ descriptions and testbenches to generate technology-specific hardware without actually modifying the algorithmic model (programming) Algorithmic Model - A method of estimating software cost using mathematical algorithms based on the parameters which are considered to be the major cost drivers. , delivering on the promise of a C++ golden source.

Pricing/Availability

The price of the Catapult C Synthesis tool currently ranges from $89,000 to $275,000. The tool is available immediately on both term and perpetual licenses. Visit http://www.mentor.com/products/c-based_design for more information.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 3,850 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon Wilsonville is a city in Clackamas County, Oregon, United States. The population was 13,991 at the 2000 census, and as of 2005 was estimated to be 16,510.[1] Geography
Wilsonville is located at  (45.306805, -122.
 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County.  95131-2314. World Wide Web site: http://www.mentor.com/.

Mentor Graphics is a registered trademark and Catapult is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
COPYRIGHT 2005 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2005, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Geographic Code:1USA
Date:May 2, 2005
Words:676
Previous Article:IDC's FutureScan: Buyers Get Realistic.
Next Article:National Technical Systems Announces the Transition of Its Executive Officers.
Topics:



Related Articles
Mentor Graphics Announces Scalable Verification Platform; New Technologies Help Bridge the Verification Gap.
Siemens Adopts Mentor Graphics Catapult C Synthesis Tool for 50 Percent Reduction in RTL Implementation of C Algorithms.
Mentor Graphics Advances Scalable Verification.
SANYO Selects Mentor Graphics Catapult C Synthesis for Next-Generation Multimedia LSI Design.
Pioneer Chooses Mentor Graphics Catapult C Synthesis Tool for R&D of Digital Signal Processing Applications.
STMicroelectronics Certifies Mentor Graphics Catapult C Synthesis Libraries and Joins Silicon Vendor Partners Program.
Mentor Graphics Introduces Catapult SL, the First High-Level Synthesis Tool to Create High-Performance Subsystems from Pure ANSI C++.
Mentor Graphics Announces New Bit-Accurate C++ Datatypes that Accelerate Algorithm Validation by 10x.
Fujitsu Microelectronics Solutions Selects Mentor Graphics Catapult Synthesis Based on Quality of Results in Wireless Communication Applications.
Mentor enables institute to offer educational opportunities for EEs.(HEAD OF THE CLASS)

Terms of use | Copyright © 2009 Farlex, Inc. | Feedback | For webmasters | Submit articles