Mentor Graphics Delivers the Next Generation of Functional Verification; Tools, Methodology and Partners Target Verification Productivity and Efficiency.WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corporation (Nasdaq:MENT) today announced its comprehensive next-generation Questa(TM) verification solution, combining tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers. The announcements include the new Questa 6.2 functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, platform, the industry's first open-source standards-based Advanced Verification Methodology (AVM AVM 1 Acute viral meningitis, see there 2 Arteriovenous malformation, see there ), and the Questa Vanguard Program (QVP QVP Quality Vendor Program QVP Quad Voice Processor (Ditech Communication) QVP Quality Verification Plan QVP Quick View Plus ), an organization of over 25 companies dedicated to helping companies build more effective verification flows. "Tools by themselves don't solve problems," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "You need standards, methodologies and an industry infrastructure that can get people up and running quickly with new capabilities. The new Questa solution addresses all of those requirements and is uniquely positioned to accelerate the adoption of the new flows that designers need." New verification techniques require a methodology The new Advanced Verification Methodology (AVM) is the first true system-level-to-RTL verification methodology. The AVM integrates advanced verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction level modeling (TLM TLM Telemetry TLM Transaction Level Modeling TLM Tout Le Monde (French) TLM The Leprosy Mission (Northern Ireland) TLM Transmission Line Matrix TLM The Little Mermaid (fairy tale) )-based framework implemented in both SystemC and SystemVerilog. Designed from the ground-up to take advantage of the new verification capabilities in SystemVerilog and SystemC, the AVM features an object-oriented coding style to reduce the amount of testbench code and a modular architecture to enable reuse. The AVM consists of the AVM Cookbook (programming) cookbook - (From amateur electronics and radio) A book of small code segments that the reader can use to do various magic things in programs. One current example is the "PostScript Language Tutorial and Cookbook" by Adobe Systems, Inc (Addison-Wesley, ISBN , a "how-to" guide for getting started, and -- an industry first -- source code for base class libraries, utilities, and implementation examples written in both SystemC and SystemVerilog. The AVM code together with the AVM documentation will be provided under an Apache 2.0 open source license. "ARM is collaborating with Mentor on a number of items to ensure interoperability between ARM(R) products and Mentor's EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. products," said Tim Holden Thomas Timothy Holden (born March 5 1957) is an American politician who has been a member of the United States House of Representatives since 1993. A Democrat, he has represented the 17th congressional district of Pennsylvania (map), having previously represented the 6th District , director of EDA Relations, ARM. "As such, our mutual customers will be able to take full advantage of a single kernel SystemVerilog / SystemC verification solution that offers performance and debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. advantages over the multi-tool, multi-language solutions." Questa 6.2 and the AVM deliver state-of-the-art verification capabilities to designers The Questa 6.2 platform is a mixed-language verification solution that supports simulation, assertions, coverage and testbench automation. Questa 6.2 includes support for all of the key components of the AVM: the object-oriented and constrained-random capabilities of SystemVerilog and SystemC, the OSCI TLM standard functionality, and the functional coverage capabilities of SystemVerilog and PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. . No other solution available today offers this broad support of advanced capabilities in standard languages. Questa adds a new, unique coverage capability to target verification efficiency Along with increases in performance and new capabilities in debugging, Questa 6.2 also includes the industry's first Unified Coverage Database (UCDB UCDB Universidade Católica Dom Bosco (Portugese) ). The UCDB eliminates the complexity of gathering and managing coverage data and consolidates all of the verification coverage data generated by the Questa 6.2 platform (including other Mentor verification technologies, such as 0-In(R) and Seamless(R) tools). With consolidated coverage analysis, designers can increase verification efficiency by identifying and eliminating wasted simulation cycles, quickly finding uncovered areas in the design, and close the verification loop by tying coverage results directly back to the original test plan. Industry partners complete the picture Without adequate industry infrastructure, no new technologies or methodologies can be successful. With the Questa Vanguard Program (QVP), Mentor has joined forces with leaders in training, consulting and verification IP to simplify and accelerate the adoption of new verification languages and techniques (see news release, "Questa Vanguard Program..." May 8, 2006). Each vendor works closely with Mentor to ensure that their products support the Questa platform and the AVM. "Today's and tomorrow's larger and more complex designs require innovative solutions. Verification remains the biggest bottleneck in design cycles making it necessary to transition to new methodologies and tools to remove the bottleneck," stated Predrag Markovic, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. Design House. "Questa offers a complete standards-based, single kernel verification environment that targets increasing verification productivity and enables the move to new methodologies like coverage-driven verification, assertion-based verification, and transaction level modeling. Questa incorporates the SystemVerilog standard, thus ensuring future reuse and design portability." Product Availability and Pricing The Questa 6.2 verification platform ships in Q2 2006 and includes access to the Advanced Verification Methodology portal. Pricing starts at $28,000 USD USD In currencies, this is the abbreviation for the U.S. Dollar. Notes: The currency market, also known as the Foreign Exchange market, is the largest financial market in the world, with a daily average volume of over US $1 trillion. . The AVM will be available in Q2 2006 at no charge under a standard, open-source license. For additional product details, call 1-800-547-3000 or go to www.mentor.com/questa About Mentor Graphics Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon Wilsonville is a city in Clackamas County, Oregon, United States. The population was 13,991 at the 2000 census, and as of 2005 was estimated to be 16,510.[1] Geography Wilsonville is located at (45.306805, -122. 97070-7777. World Wide Web site: http://www.mentor.com/. Mentor Graphics, 0-In and Seamless are registered trademarks and Questa is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners. |
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