Marvell Announces the World's First and Most Advanced 8-Port DSP Fast Ethernet PHY Transceiver.SUNNYVALE, Calif.--(BUSINESS WIRE)--Sept. 27, 1999-- 0.25um DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive 10/100 Octal PHY See physical layer and physical. Sets New Performance Benchmarks For Highest SNR See signal-to-noise ratio. SNR - signal-to-noise ratio , Distance Coverage/Connection Reliability & Low Power Consumption Marvell Semiconductor Inc., a leading provider of high performance mixed-signal DSP integrated circuits for processing complex real world communications signals, today announced the world's first and most advanced 8-port (Octal) DSP 10/100 Fast Ethernet transceiver. The Marvell M88E3080 breaks new ground in low-power dissipation, higher Signal-to-Noise ratios and distance coverage/connection reliability. The introduction of the Fast Ethernet transceiver product is part of an aggressive, broad-based R&D effort by Marvell to develop a new class of DSP-based Gigabit Ethernet PHY technology and products. Marvell announced that it is sampling its first family of 0.25um DSP 10/100 Octal Fast Ethernet physical layer device (PHY) transceivers, with full production expected in the fourth quarter of 1999 and initial customer design wins already achieved. With today's announcement, Marvell brings its proven mixed-signal DSP processing technology solutions to the broadband data networking communications market to help enable a new era of high bandwidth applications. "As the leading supplier of high-performance mixed-signal DSP solutions with leading edge communications algorithm expertise and advanced circuitry, Marvell is uniquely qualified to meet the demands of the next generation of broadband networking," said Dr. Sehat Sutardja, Marvell's president and chief executive officer. "The new M88E3080 sets new milestones for performance, reliability and cost-effectiveness in the high-speed Ethernet market and represents a major step in the development of our DSP-based Gigabit Ethernet technology and products." The Marvell M88E3080 Octal DSP PHY Transceiver sets several new performance benchmarks in areas such as:
- Marvell M88E3080 core utilizes patented analog to digital
conversion technology providing for dramatically higher
Signal-to-Noise ratio - up to 3dB better than existing DSP PHY
solutions
- Up to 200m of distance coverage -- Advanced DSP algorithms
derived from the industry's highest performance Partial Response
Maximum Likelihood (PRML) read channel technology results in the
most reliable connection
- The industry's highest density interface with up to double the
number of ports per box
- The industry's lowest power dissipation device for PHY designs
compared to existing DSP solutions
- The first physical layer device with integrated low drop-out
voltage regulator for applications in which only a 3.3 voltage
supply is present
Advanced DSP The Marvell M88E3080 integrates eight identical DSP-based Fast Ethernet transceivers. The device utilizes advanced signal processing algorithms and high performance self-calibrating analog front-end technology originally deployed in Marvell's PRML (Partial Response Maximum Likelihood) A technique used to differentiate a valid signal from noise by measuring the rate of change at various intervals of the rising waveform. read channel devices running at more than 600MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. clock frequency. The M88E3080 device is implemented in an advanced 0.25um digital CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. process. Unlike traditional analog implementations, Marvell's self-calibrated analog front-end and fully adaptive DSP back-end readily compensate for variations in normal IC processing, die temperatures, supply voltages and even component level mismatches, resulting in devices with more consistent performance levels. Improved Connection Reliability Marvell's DSP Fast Ethernet PHY transceiver successfully addresses one of the most challenging problems faced by IT managers -- dealing with cabling networks that barely or questionably meet the CAT5 specifications. Marvell's advanced DSP technology results in more robust physical layer devices that are more tolerant to variations in network cabling infrastructures, such as those found in installations using lower cost UTP UTP (uridine triphosphate): see uracil. (Unshielded Twisted Pair) See twisted pair. UTP - unshielded twisted pair CAT5 cable. These enhancements allow customers to minimize support costs. "This feature will represent a significant point of differentiation for Marvell. By dramatically improving the robustness of physical layer devices, we are helping IT managers build the most reliable network," Sutardja noted. Additional Benefits The M88E3080 is offered in a compact 208-pin PQFP (Plastic Quad Flat Package) Refers to many varieties of QFP chip packages, which are molded in plastic. See QFP. package, which has been optimized for the highest port count density and shortest distance connections to the quad magnetic modules and the RJ-45 connectors. Short connections produce lower parasitic capacitances, improving return loss characteristics and enabling the use of standard low-cost quad magnetics. Lower power designs reduce the amount of power needed to implement high-density switch applications to about half of the traditional solutions. Lower power dissipation translates into lower cost power supply systems, higher system reliability, reduced fan cooling, and in most instances no fan cooling requirements. The M88E3080 device supports both the Reduced Media Independent Interface Reduced Media Independent Interface (RMII) is a standard that addresses the connection of Ethernet physical layer transceivers (PHY) to Ethernet switches. It reduces the number of signals/pins required for connecting to the PHY from 16 (for an MII-compliant interface) to 6 to 10. (RMII RMII Reduced Media-Independent Interface RMII Rocky Mountain Internet Inc. ) and Serial Media Independent Interface (SMII SMII Serial Media Independent Interface ). The 0.25um core is also available for integration with customer specific intellectual property to address high volume yet low cost proprietary solutions. "The Marvell ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. team is ready to accept customer specific designs using industry standard design methodology," Sutardja added. About Marvell A subsidiary of Marvell Technology Group Marvell (NASDAQ: MRVL) is an American producer of storage, communications and consumer semiconductor products. Their products can be found in a range of applications:
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