Manufacturing considerations of embedded passives; designing and building PCBs with EPs means knowing the tolerances of the different material sets.

AS I CONTINUE with my objective of helping stimulate the adoption of embedded passive technology by systematically providing a collection of useful reference materials for the future adaptors, I feel the next appropriate step is providing an understanding of the PCB manufacturing process considerations as they relate to the various EP material sets. Understanding manufacturing process tolerances will enhance designing and embedding resistors and capacitors.

Following is a nutshell overview of the multilayer PCB manufacturing processes. These can be categorized as photographic, chemical or mechanical. First we convert CAD-created image data into tooling. The tooling enables the transfer of the image to the PCB materials. The photographic processes--commonly referred to as imaging--and the chemical processes--primarily plating and etching-are methods for creating images and forming 3D wiring features. The mechanical processes--laminating the layers together and drilling holes--and the chemical processes--plating the drilled holes and plating and etching the outerlayer circuits--complete the multilayered 3D wiring matrix. This is our MLB, multilayer printed board.

Building MLBs involves nine basic image process steps, each with its own (predictable) tolerance. These are: CAD inputs and conversion, laser plotter accuracy, Mylar film stability, innerlayer side-to-side, outerlayer phototool punching, post-etch laminate shrinkage (after scaling), post-etch tooling hole punching, lamination pinning, and laminate instability during pressing. Without elaborating on each step, the sum of the nominal tolerances for the conventional PCB process is about +/-0.009-. This is the worst case. The largest contributor is post-etch laminate shrinkage, which can be up to +/-0.003", and that is after scaling artwork. This tolerance is affected by inherent characteristics of the copper-clad laminate. These are induced by the materials and laminate manufacturing process, including the type of reinforcement, type of resin, copper weight and curing conditions. For some constructions, the shrinkage is as much as 0.040" across a 24" panel. Other constructions may be as little as 0.002" for the same panel size. To complicate matters, some constructions actually grow rather than shrink.

At this point the reader might wonder, how is it possible to successfully manufacture boards with such extreme tolerances? Without exception, all PCB manufacturers scale artwork based on the predicted shrinkage/growth of the laminate material after etch and lamination. Scaling means to transfer a larger/smaller image to the copper clad laminate such that after etch, it will grow/shrink to size. (Fabricators would benefit enormously if their suppliers made "sanforized" laminates.) However, once the laminate material is characterized, its shrinkage/growth behavior is reasonably predictable. The reality is that tolerances do not all go in one direction, so statistically any point of our image (after scaling) will fall within +/-0.003" of where we want it. Coincidentally, this value (0.003") is approximately twice the RMS of the worst-case tolerances. The tolerances for these processes are well established per IPC-2221, "Generic Standard on Printed Board Design."

TABLE 1 shows the additional process steps required for the various material sets. These are organized in the same manner as in last month's column.

The common thread in these additional steps is that they all use standard processes and they all must integrate with any EP-containing layer(s). Further, the additional steps required all involve secondary imaging on previously processed material, some on etched innerlayers and some with more complex ceramic image processes involving firing on copper foil. This explains why process tolerances between the primary conventional MLB image and the secondary image (EP image) is crucial. These tolerances are the basis for the size, positioning and termination of the EP component. TABLE 2 shows the recommended design allowance. This allowance may be thought of as the additional size of the copper termination feature over the EP feature to ensure proper continuity. FIGURE 1 illustrates the relative size and position of the tolerance zones.

[FIGURE 1 OMITTED]

The essence of this tolerancing scheme is that as the primary and secondary images are merged, there must be sufficient overlap to ensure that terminations are adequate. This must be taken up in the size and positioning of the primary PCB image and secondary EP image. The message to the designer is that the manufacturing tolerances affect the design and are the basis for the size, positioning and termination of the embedded passive part.

Please feel free to contact me with any questions on this concept.

TABLE 1. Process Steps for Various EP Materials

CONVENTIONAL PROCESSES                ADDITIONAL PROCESS STEPS

PHOTOPRINT AND ETCH: METAL THIN-FILM RESISTORS

All standard PCB/MLB processes used   Standard print-and-etch layer
                                      per design
Integrate with resistor layer(s)      Second photoprint and develop
                                      resist to define resistor
                                      and unwanted resistive material
                                      Etch unwanted resistive material
                                      Strip resist
                                      Trim, if required
                                      Test resistors
                                      Screen print protective coating
                                      on resistor

SCREEN PRINT: POLYMER THICK-FILM (PTF) RESISTORS

All standard PCB/MLB processes used   Standard print-and-etch resistor
                                      layer per design
Integrate with resistor layer/s       Print/develop photoresist to
                                      define resistor termination pads
                                      Apply electroless silver coating
                                      Strip resist
                                      Trim, it required
                                      Test resistors

ETCHED COPPER PLANES: PLANAR CAPACITORS

All standard PCB/MLB processes used   Thin-core processing
                                      Transport
                                      Handling
Power and ground plane pairs          In process hi-pot testing
become a capacitor
Treated like manufacturing power      Some materials require sequential
and ground plane cores                lamination, which adds cost and
                                      registration issues to the
                                      process
Thin-core processing                  No process limitations for the
                                      majority of PCB manufacturers

SCREEN PRINT: CERAMIC THICK-FILM (CTF) RESISTORS AND CAPACITORS

All standard PCB/MLB processes used   Unique CTF image and firing
                                      process
Integrate with CTF core structure     Resistor/capacitor pastes printed
                                      and fired on copper foil
                                      Requires firing in [N.sub.2] at
                                      900[degrees]C
                                      Foil laminated into CTF core
                                      structure
                                      Special scaling and registration
                                      to integrate into conventional
                                      PCB/MLB processes
                                      Print and etch CTF core
                                      structures that terminate
                                      resistors and define circuit
                                      patterns
                                      Laser trim
                                      Test resistors/capacitors

TABLE 2. Recommended Design Allowance

WORST CASE IMAGE TOLERANCES       RECOMMENDED
                                  DESIGN ALLOWANCE

PRIMARY IMAGE   SECONDARY IMAGE

Photoprint and etch: metal thin-film resistors

+/-0.009"       +/-0.004"         +/-0.003"

Screen print: PTF resistors

+/-0.009"       +/-0.004"         +/-0.004"

Etched copper planes: planar capacitors

+/-0.009"       NA                IPC-2221

Screen print: CTF resistors and capacitors

+/-0.009"       +/-0.010"         +/-0.005"

* Sum of tolerances of all of the individual process steps.

RICHARD SNOGREN is a member of the technical staff at

Coretec Inc. (coretec-inc.com). He can be reached at

[e-mail].