Managing CSP underfill processes: the inherent slowness of underfill flowout can be masked to improve throughput.

In handheld products like cell phones, camcorders, personal digital assistants (PDAs), global positioning system (GPS) units and mobile computers, chip-scale packages (CSPs) enable density and functionality in a small package. A CSP is typically defined as 1.2 times the size of a bare die. New stacked CSPs allow packing densities of greater than 100 percent. Board assembly operations can pick and place these new CSPs using standard surface-mount equipment, and the infrastructure and methods exist for testing prior to assembly. The result is a geometric growth of the use of CSPs for all types of electronic components.

When handheld devices are accidentally dropped, the stresses can fracture the CSP solder joints or at least cause crack initiation, which will cause a later failure. Underfill bonds the CSPs to the board and helps distribute this stress over a much larger surface area. Unlike flip chip, the thermal characteristics are not the goal of underfill with CSPs; the goal is to improve resistance to shock and vibration. Engineers are continuing to explore methods to underfill and how to minimize the cost, cycle time and complexity.

Fortunately for surface-mount manufacturers, existing solutions for flip chip underfill are well developed and can be used to dramatically improve the reliability of CSPs. Pumps exist to handle the material stability issues such as viscosity change with time; for example, the linear positive displacement pump. Statistical process control (SPC) and set-up for weight-controlled lines are well developed methods used with mass flow control calibration. Heated tooling also exists to lower the viscosity and accelerate the underfill flowout, thereby reducing the overall underfill time.

Underfill dispensing has now evolved so that dispense time represents a very small portion of the total process time. The time needed for encapsulant to flow out beneath the chip is invariably the largest factor. Current process improvement efforts now focus on reducing overall underfill cycle times by managing the flowout time. A combination of techniques yields results: concurrent interleaving of dispensing and flowout operations; staging boards in pre-and post-dispense heat; and management of the amount and time that heat is applied. This article discusses the use of underfill for CSPs and the new techniques for optimizing flowout times and overall throughput rates.

Underfill Dispensing Techniques

The underfill dispensing process can be smoothly integrated after reflow within the surface-mount line, thereby enabling upstream and downstream processes to run at high speed. Because the dispensing step comes after reflow, some manufacturers may choose to insert an electrical testing step prior to the underfill encapsulation step. This testing checks the solder joints and CSP functionality to improve yields, although reworkable CSP underfills are now available.

CSP underfill dispensing also must cope with dispensing around components placed in the path of the dispense needle or through radio frequency (RF) shields. Multi-chip CSP designs are often tightly packed with many chip components and connectors. Larger needle diameters can have greater flow rates, hence quick dispense times. If the dispense path is narrowed by adjacent components being placed close to the CSPs, the dispensing process will require a smaller needle diameter to dispense between and around the devices, which will increase the total dispense time. Needle positioning, motion and flow rate must be controlled to avoid risk of adhesive flowing onto adjacent components.

To meet these requirements, the underfill dispenser must have:

* the ability to coordinate x and y motions with heaters, pumps and weight-controlled lines at specific times

* linear positive displacement pump control

* precise control over weight of a dispensed line

* flexible, simple programming that allows for the correct flowout delays.

Dispensing patterns such as the single line, the L-pass and the seal pass have evolved over years of experience in chip-level environments. (1) CSPs generally require an L-pass for optimal throughput. However, the L-pass may not be possible with RF shields, which usually require several small shots of material to be dispensed through a hole in the top of the shield.

The Flowout Bottleneck

With today's modern systems, dispensing speeds have greatly improved to several hundred milligrams per second (mg/s). However, the overall underfill encapsulation process must also take into account the challenges of minimizing flowout time for multi-pass dispensing sequences.

From a total time-per-assembly perspective, dispensing itself is a relatively small part of the throughput equation (Figure 1). Today's dispensing systems can consistently run much faster than the flowout process. For example, an L-pass on a 12 mm x 12 mm CSP takes about 0.5 seconds to dispense. However, the time required for the encapsulant to flow out under the die can take as much as 10 or more seconds. Even when including 4 seconds for board loading, 1 second for fiducial acquisition and 2 seconds for moving/positioning the dispensing head, the flowout time still represents over 70 percent of the total cycle time.

Dual-Lane Dispensing

Using dual conveyor lanes in the dispensing process significantly boosts throughput rates for underfill by enabling the dispense head to alternate passes between multiple assemblies, which masks flowout time. Dual-lane dispensing systems also mask board transfer time, but this factor is less significant than masking flowout time (Figure 2).

Masking flowout can deliver dramatic throughput increases. However, dual-lane dispensing has mixed acceptance in surface-mount assembly because the emphasis has been on masking board transfer times. The drawback is that board transfer is usually only the time required to convey the board into the machine, which is typically 3 to 5 seconds per cycle. In contrast, flowout time can be four times as long, so that masking flowout saves up to 20 seconds per cycle. Combined with pre-and post-dispense heat operations, masking flowout can nearly double throughput in boards requiring multiple fills or in any assemblies that require multiple shots (Figure 3).

[FIGURE 3 OMITTED]

A quick estimate of the potential savings can be made by timing the flowout and comparing to total cycle time. For example, if flowout accounts for 50 percent of the process time for a board at the dispense station, then a maximum benefit of 2x can be obtained in throughput with a dual-lane system, assuming that a second dispense or seal pass is required. If flowout takes longer than 50 percent of the process time, then more lanes would be required to maximize throughput.

When smaller fillets of material are required to minimize the board space used, a smaller needle can be used. However, this approach may require multiple dispense cycles of a smaller weight; for example, 30 mg can be split into 3 x 10 mg lines of material. This approach will allow board designers to put test points closer to a CSP on an assembly, thereby minimizing the danger of overcoating with underfill.

On assemblies where the dispense head has to wait between multiple passes, dual-lane dispensing can reduce the process time by allowing the dispense head to immediately jump to assemblies in the second lane after underfilling those in the first lane (Figure 4). For complex designs with multiple devices on the same substrate or small CSP assemblies ganged together, the ability to get more parts into the work envelope enables flowout to be spread over even more dispensing passes, thereby raising the ratio of dispense time to flowout time.

[FIGURE 4 OMITTED]

To effectively use dual-lane processing, the system must maximize the actual dispensing time and eliminate the wait for flowout. A high degree of machine programmability and multi tasking flexibility is required to deliver optimal utilization and throughput rates for specific product configurations. When boards go into the dispensing area, the system must automatically find all fiducials and height-sensing data for both lanes. This capability enables subsequent interleaved dispensing operations to be conducted in a single seamless process flow.

Temperature Management

Because flowout time can be a large part of the CSP underfill cycle time, thermal management of the dispense process is critical. Two primary aspects to thermal management must be addressed: obtaining and maintaining proper temperatures in the different stages of the process; and improving ramp time of the product in a high-throughput production environment.

The optimal dispense and curing temperatures must be achieved to improve the flow characteristics within a reduced time window. Carefully controlled heat levels significantly speed flowout. The process temperatures must be achieved consistently and repeatedly to avoid inconsistencies or defects. Temperature gradients due to poorly designed heat delivery systems can affect capillary flowout patterns in undesirable ways. Proper patterning of contact areas with conductive heating devices, or vent hole patterns when utilizing impingement or convective air-heating devices, will eliminate voids and speed flowout time. Accurate temperature control of the heating devices will maintain the process temperatures from one component to another, thereby improving overall yield.

As the pressure to improve cycle times increases, the advantages of staging the process into pre-dispense, dispense and post-dispense become important. Simultaneously, process temperatures can be achieved at the pre-dispense station and flowout can be thermally controlled at post-dispense, while components are being processed at the dispense station (Figure 5). Fast ramp times can also improve the overall board cycle time. With careful temperature control and system timing, the pre-dispense station can be used to quickly elevate the board temperature. However, the ramifications of overheating the part when employing fast ramp-time techniques must be considered.

[FIGURE 5 OMITTED]

As dispense technology improves, the flowout time becomes more critical to throughput. Thermal management can play a key role in improving cycle times.

Conclusion

Underfilling CSPs on boards is becoming common, and understanding the best dispense methods is an important part of surface-mount production environments. Board-level manufacturers must thoroughly understand the critical differences between the dispensing and flowout aspects of the overall process. Instead of simply thinking of underfill as a characteristically slow process that must be endured, savvy process engineers are taking maximum advantage of new-generation dispensing systems and dual-lane processing to effectively mask the inherent slowness of underfill flowout.

FIGURE 1: CSP cycle time in a single-lane system.

Flowout           48%
Fiducial           7%
Read
Dispense           3%
Positioning       14%
Motion
Board Transfer    28%

Note: Table made from pie chart.

FIGURE 2: CSP cycle time in a dual-lane system.

Board Transfer        27%
board #2
Fiducial Read          7%
board #1
Dispense board #1      3%
Positioning Motion    13%
board #1
Board Transfer        27%
board #1
Fiducial Read          7%
Board #2
Dispense board #2      3%
Positioning Motion    13%
board #2

Note: Table made from pie chart.

Industry Terms

ASIC    Application-Specific Integrated Circuit
ASIP    Application-Specific Integrated Passive
BGA                             Ball Grid Array
COB                               Chip On Board
CSP                          Chip-Scale Package
CTE            Coefficient of Thermal Expansion
DCA                          Direct Chip Attach
DIP                         Dual Inline Package
IC                           Integrated Circuit
I/O                                Input/Output
MCIC      Multilayer Ceramic Integrated Circuit
MCM                           Multi-Chip Module
MCP                          Multi-Chip Package
PBGA                    Plastic Ball Grid Array
PWB                        Printed Wiring Board
QFP                           Quad Flat Package
QSOP                 Quad Small Outline Package
RF                              Radio Frequency
RFIC         Radio Frequency Integrated Circuit
SCP                         Single Chip Package
SOC                              System On Chip
SOIC           Small Outline Integrated Circuit
TCC      Temperature Coefficient of Capacitance
TCE        Temperature Coefficient of Expansion
TCR       Temperature Coefficient of Resistance

NOTE: These industry terms are from the 2000 NEMI Technology Roadmap For
further information, contact the National Electronics Manufacturing
Initiative at www.nemi.org.

References

(1.) Carbin, J., et al, 1999. Underfill and encapsulation. Advanced Packaging. May.

Steven J. Adamson is product manager, Barry Wheatley is tool specialist and Frank Murch is director of marketing, all with Asymtek, Carlsbad, CA; e-mail: [e-mail].