Magma and Mentor Graphics Deliver Integrated Test Solution for Blast Chip Users.Business/Technology Editors CUPERTINO, Calif.--(BUSINESS WIRE)--June 11, 2001 Magma Design Automation Magma Design Automation (NASDAQ: LAVA) is a software company in the electronic design automation (EDA) industry. The company was founded in 1997 and maintains headquarters in San Jose, California. , Inc. and Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. Corporation today announced the availability of an integrated design The introduction to this article provides insufficient context for those unfamiliar with the subject matter. Please help [ improve the introduction] to meet Wikipedia's layout standards. You can discuss the issue on the talk page. implementation and test solution. More than an interoperability effort, the companies have worked together to identify and implement new capabilities within Magma's Blast Chip(TM) RTL-to-silicon system, streamlining the interface to the Mentor Graphics(R) DFTAdvisor(TM) testability analysis and test synthesis tool. The new Magma technology provides integrated access to DFTAdvisor, while preserving Blast Chip's unique layout-to-RTL cross-probing capabilities. The solution combines the extremely fast and high capacity logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. of Blast Chip with the comprehensive design-for-test (DFT DFT - discrete Fourier transform ) analysis and test synthesis of DFTAdvisor, providing reduced turn-around-time and a highly predictable design flow. Customers also benefit from easy access to FastScan(TM) 2001, the industry's premier automatic test pattern generation ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital (ATPG ATPG Automatic Test Pattern Generation ATPG Automatic Test Program Generator ) tool, through its automatic integration with the DFTAdvisor tool. "Design-for-test is a key component of the design and implementation flow for complex, deep submicron chips," remarked Bob Smith vice president of marketing and business development for Magma Design Automation. "By teaming up with Mentor we are able to offer the best of both worlds --- an accelerated chip implementation flow that includes powerful design-for-test tools. This will enable our mutual customers to shorten their design cycles and improve the testability and, ultimately, the quality of their manufactured chips." "We are pleased to be working with Magma on this integrated solution," said Lori Watrous-deVersterre, general manager, Design-for-Test division, Mentor Graphics. "The combination of Mentor's DFT products with Magma's RTL-to-silicon system provides a comprehensive design environment that today's designers are looking for Looking for In the context of general equities, this describing a buy interest in which a dealer is asked to offer stock, often involving a capital commitment. Antithesis of in touch with. . This integration allows our joint customers to focus on their critical design issues rather than tool integration issues." Using this flow, a netlist is quickly generated by Blast Chip and can be imported into DFTAdvisor. Any DFT errors detected in the synthesized netlist can be either fixed manually by editing the RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; or automatically fixed using DFTAdvisor. Once all DFT design rules have been corrected and scan logic inserted by DFTAdvisor, a new netlist is generated and loaded into Blast Chip using an ECO E·co , Umberto Born 1932. Italian writer best known for his novels, including The Name of the Rose (1981). He has also written extensively on semiotics and British and American popular culture. process to complete the physical design. Meanwhile, ATPG can be run using FastScan. This integrated solution is available now. For more information, visit the Magma demo suite #4345 at the Design Automation Conference at the Las Vegas Convention Center The Las Vegas Convention Center is owned and operated by the Las Vegas Convention and Visitors Authority and is located in Clark County, Nevada. It is one of the largest Convention centers in the world. At the end of 2004, the center had 3. in Las Vegas Las Vegas (läs vā`gəs), city (1990 pop. 258,295), seat of Clark co., S Nev.; inc. 1911. It is the largest city in Nevada and the center of one of the fastest-growing urban areas in the United States. June 18 - 21, 2001. About Blast Fusion and Blast Chip Magma's design and implementation solutions include our flagship product Blast Fusion (TM) and Blast Chip (TM). Blast Fusion is a comprehensive, highly integrated physical design system. Unlike traditional point tool solutions, Blast Fusion is a single system containing design and optimization engines and analysis tools that operate on a single data model. Blast Fusion uses a single, incremental timing analyzer throughout the flow and the system's clock tree implementation technology allows the user to either minimize skew (1) The misalignment of a document or punch card in the feed tray or hopper that prohibits it from being scanned or read properly. (2) In facsimile, the difference in rectangularity between the received and transmitted page. or use skew to improve clock performance. This tight integration of the tools and single data model architecture enable Blast Fusion to efficiently handle complex designs. Blast Chip includes all the capabilities of Blast Fusion plus RTL synthesis. Blast Chip is the only system able to take designs from RTL to GDSII GDSII Graphic Design System II through one truly integrated flow. Both Blast Fusion and Blast Chip enable the design of large systems on a chip (SoC) incorporating tens of millions of transistors. About DFTAdvisor and FastScan 2001 The DFTAdvisor test synthesis tool expedites test efforts by automatically inserting full or partial internal scan and test logic structures into designs and automating scan synthesis. Its exhaustive analysis identifies and corrects testability problems before the test generation design phase. By addressing testability analysis early in the design process, DFTAdvisor enables users to avoid costly fixes downstream and ensures high-quality testable designs. DFTAdvisor automatically adds test logic to correct problems with design testability, providing control of such things as internally-generated clocks, sets and resets which do not comply with scan design rules. Mentor's FastScan 2001 ATPG tool creates high-quality manufacturing test patterns for today's most complex designs. With capabilities for stuck-at, IDDQ IDDQ Indefinite Delivery Definite Quantity IDDQ Integrated Circuit Quiescent Current , and at-speed test generation, FastScan 2001 creates the highest quality test sets available today. Furthermore, with new capabilities in both pattern compression and pattern optimization FastScan creates the most compact test set possible so that cost-of-test is minimized. The FastScan tool suite also includes FastScan Diagnostics for the analysis of failing patterns to isolate defects during failure analysis, and FastScan MacroTest, which creates scan-based tests for small, embedded blocks and memories. FastScan 2001 and DFTAdvisor compliment the most comprehensive DFT tool suite of any EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. supplier in the market, which also includes solutions for logic BIST BIST - Built-in Self Test , memory BIST, boundary scan, sequential ATPG and graphical testability debugging. For more information, visit www.mentor.com/dft. About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 2,850 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. 95131-2314. World Wide Web site: www.mentor.com. About Magma Magma Design Automation provides design and implementation software that enables chip designers to shorten the time-to-market for complex integrated circuits used in the communications, computing, consumer electronics, networking and semiconductor industries. The company's products, Blast Fusion(TM) and Blast Chip(TM), utilize a new methodology for the design of complex multi-million gate chips by combining traditionally separate front-end and back-end In their most general meanings, the terms front end and back end refer to the initial and the end stages of a process flow. These terms acquire more special meanings in particular areas. design processes into an integrated design flow. This integrated solution reduces timing closure iterations, which accelerates time-to-market for its customers. Magma's proprietary FixedTiming(TM) methodology and single data model architecture serve as the technical foundation for the Blast Fusion and Blast Chip products. FixedTiming enables Magma's products to optimize for timing performance throughout the flow, predict circuit speed before detailed physical design, and deliver final timing that approximates the predicted circuit speed. The single data model architecture contains and manages the logical and physical data for the chip design, allowing Magma's products to shorten the design cycle and increase the efficiency of the design process. In addition to the design and implementation products, Magma's Blast Noise(TM) product analyzes and corrects integrated circuits for noise problems that may impact chip performance. Headquartered in Cupertino, Calif., the company maintains sales and support offices in Silicon Valley, Austin, Boston, Germany, Israel, Japan, Korea, Taiwan and the United Kingdom. Corporate headquarters are at 2 Results Way, Cupertino, Calif., 95014. Visit Magma Design Automation on the web at www.magma-da.com. Blast Chip, Blast Fusion, Blast Noise, FixedTiming and Magma are trademarks of Magma Design Automation. All other product and company names are trademarks and registered trademarks of their respective companies. Mentor Graphics is a registered trademark and FastScan and DFTAdvisor are trademarks of Mentor Graphics Corporation. All other product and company names are trademarks and registered trademarks of their respective owners. |
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