Magma Announces Blast Plan for Complex Chip and SOC Design Planning; Data Reduction Methodology Allows Large Designs to be Handled Efficiently Without Sacrificing Accuracy.
At DAC Booth #807
CUPERTINO, Calif.--(BUSINESS WIRE)--June 11, 2001
Magma Design Automation, Inc., a provider of chip design solutions, today introduced Blast Plan(TM) a new product that delivers hierarchical design planning capabilities for use in implementing complex integrated circuit and system-on-chip (SoC) designs. Blast Plan leverages the capabilities of Magma's existing Blast Fusion(TM) and Blast Chip(TM) systems to streamline the hierarchical planning and design of very large chips and SoCs within a single environment, eliminating the numerous, cumbersome and error-prone data transfers between point tools in traditional flows. In addition, Blast Plan supports design blocks and intellectual property (IP) that have been created using external flows.
Magma's Blast Fusion and Blast Chip systems already contain the basic tools needed for bottom-up hierarchical chip assembly. These include floorplanning, I/O placement, macro placement, and physical abstraction capabilities. Blast Plan adds significantly to these by providing a suite of top-down planning and design capabilities including partitioning, pin assignment and optimization, time budgeting, hierarchical floorplanning, and timing abstraction. In addition, Blast Plan's data reduction and abstraction methodologies allow massive designs to be handled efficiently without sacrificing accuracy. Coupled with the existing bottom-up capabilities of Blast Fusion and Blast Chip, Blast Plan's new features enable a complete and open flow for the hierarchical design of complex chips and SoC designs.
"Our Blast Fusion and Blast Chip products already have the capacity to handle flat designs or blocks of several million gates," said Bob Smith, vice president of marketing and business development at Magma. "By adding Blast Plan we are looking towards the future and providing an integrated hierarchical planning and design environment today that will scale well up into the tens of millions of gates."
Automated Top-Down Planning Tools
Blast Plan's top-down planning tools enable design teams to plan and manage the creation of very large chips and SoCs using a hierarchical methodology. Automated design partitioning assists designers in quickly arriving at the optimal partitioning for the entire chip. This feature is based on a massive placement algorithm that develops a global placement for the chip, including macros and IP blocks. Based on this placement, the team can quickly identify the optimal partitions for the project and define the hierarchical blocks that will make up the design.
Automated pin optimization and interactive pin assignment are provided to assign optimal pin locations for each block in the design. Automatic time budgeting is performed by first running a gain-based optimization, based on Magma's FixedTiming(TM) methodology, on the interface paths between blocks. This is followed by a timing snapshot that produces accurate and realizable time budgets. Based on these budgets, boundary constraints are generated for each block in the design that will be used in guiding the implementation of the individual blocks.
Data Reduction Methodology and Chip Assembly
A challenge in implementing very large designs is the overwhelming amount of data that must be managed throughout the process. Magma's hierarchical solution relies heavily on data reduction techniques to minimize the amount of data required at various stages in the flow without sacrificing accuracy. Data reduction techniques are applied to completed hierarchical blocks to yield "glassbox" models. These compact, memory-efficient models retain the full timing and layout extraction accuracy of the entire block without having to retain the full detail of the block contents. This approach provides a very efficient means for optimizing the global timing and chip assembly at the top-level of the design without consuming large amounts of memory.
Chip assembly is completed by performing optimization and buffer insertion at the top-level of the design and completing the top-level routing using either Blast Fusion or Blast Chip. Magma's router operates in both gridded or virtual gridless modes and is used for both detail routing at the block level as well as the top-level routing for chip assembly. This eliminates the need to have separate routing engines for these tasks.
Magma's hierarchical system supports the use of IP that comes from other chip design flows and can import and export design data in industry standard formats for logical, physical and timing data. This open approach simplifies the integration of Magma's systems into existing flows. Data management within the Magma flow itself is vastly simplified since the entire system is built around a single data model. In conventional flows, there are many different data types and formats that need to be managed between the various point tools in the flow. All data in the Magma hierarchical flow is captured in one binary object called a "volcano." The volcano contains all of the relevant design information at that point in the flow including logical, physical, and/or timing data. For example, after Blast Fusion completes the detailed implementation of a block, a volcano containing the glassbox representation of the block will be generated and used as input for the subsequent chip assembly step.
Pricing and Availability
Blast Plan is available for both the Solaris and Linux operating systems. It is currently in beta testing with full production scheduled for the third quarter of calendar 2001. Pricing starts at $104,167. Contact Bob Smith for more details. He can be reached via email at firstname.lastname@example.org or at (408) 864-2020.
For more information, visit Magma at the Design Automation Conference in Las Vegas June 18 - 21, 2001 in the Las Vegas Convention Center. Its complete line of chip design systems will be demonstrated in the Company's booth, number 807. To register for suite demos, visit the website at www.magma-da.com. Or, attend the DAC Exhibitor Presentation Monday, June 18, 2001 at 4 p.m. in Room N109-N112.
Magma Design Automation provides design and implementation software that enables chip designers to shorten the time-to-market for complex integrated circuits used in the communications, computing, consumer electronics, networking and semiconductor industries. The company's products, Blast Fusion(TM) and Blast Chip(TM), utilize a new methodology for the design of complex multi-million gate chips by combining traditionally separate front-end and back-end design processes into an integrated design flow. This integrated solution reduces timing closure iterations, which accelerates time-to-market for its customers. Magma's proprietary FixedTiming(TM) methodology and single data model architecture serve as the technical foundation for the Blast Fusion and Blast Chip products. FixedTiming enables Magma's products to optimize for timing performance throughout the flow, predict circuit speed before detailed physical design, and deliver final timing that approximates the predicted circuit speed. The single data model architecture contains and manages the logical and physical data for the chip design, allowing Magma's products to shorten the design cycle and increase the efficiency of the design process. In addition to the design and implementation products, Magma's Blast Noise(TM) product analyzes and corrects integrated circuits for noise problems that may impact chip performance.
Headquartered in Cupertino, Calif., the company maintains sales and support offices in Silicon Valley, Austin, Boston, Germany, Israel, Japan, Korea, Taiwan and the United Kingdom. Corporate headquarters are at 2 Results Way, Cupertino, Calif., 95014. Visit Magma Design Automation on the web at www.magma-da.com.
Blast Chip, Blast Fusion, Blast Noise, Blast Plan, FixedTiming, and Magma are trademarks of Magma Design Automation. All other product and company names are trademarks and registered trademarks of their respective companies.