MIPS Technologies Launches Next-generation Family of 32-Bit Cores.Business/Technology Editors
SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--June 11, 2001
MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. 32(TM) 4KE(TM) Family Offers Highest Performance Available
in Synthesizable 32-Bit Cores; LSI LSI: see integrated circuit.
(Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. Logic Among the First Licensees
(Embedded Processor A CPU chip used in a system other than a general purpose workstation, desktop or laptop computer. Such chips are used by the billions every year in a myriad of products. See embedded system. Forum) MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), a leading provider of industry-standard 32- and 64-bit processor architectures and cores for digital consumer and network applications, today launched the next generation of its 32-bit, high-performance, low-power cores, the MIPS32(TM) 4KE(TM) family. It offers the highest Dhrystone MIPS/MHz performance available in a synthesizable 32-bit core.
The 4KE family not only offers 1.4 Dhrystone MIPS/MHz, but also provides configurable features that increase performance while reducing die size and power consumption and, ultimately, total system cost. Features such as 128 kilobytes of cache and a coprocessor coprocessor
Additional processor used in some personal computers to perform specialized tasks such as extensive arithmetic calculations or processing of graphical displays. interface allow users to easily configure a 4KE core to maximize performance in their system-on-chip (SoC) applications. MIPS16e(TM) code compression can reduce memory requirements by up to 40 percent, and extensive clock gating significantly reduces power consumption. And, because the 4KE cores are synthesizable, enabling easy integration into SoC designs, they are a cost-effective, quick time-to-market solution for digital consumer applications, from ultralow-power mobile devices to emerging home networking products.
LSI Logic (NYSE NYSE
See: New York Stock Exchange : LSI), one of the world's leading ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. providers and a longstanding MIPS Technologies' licensee, is one of the first companies to take a license of a core in the 4KE family, specifically the 4KEc(TM) core.
"This new generation of MIPS cores takes our 32-bit portfolio to new heights of performance, flexibility and lower system cost by offering customers a configurable, high-performance, low-power solution for a variety of applications, including consumer, business-systems and networking," said Rafi Kedem, senior director of processor cores at LSI Logic Corp.
"The 4KE family represents a major milestone in our MIPS32 technology roadmap by giving MIPS licensees a whole new level of performance and flexibility, with features that allow them to maximize performance and power efficiency, reduce die size, lower overall system cost and create a competitive advantage for their product," said Victor Peng, vice president of engineering at MIPS Technologies.
Other features of the 4KE family include:
-- Reference process: 0.13 micron -- Typical performance: 340 MHz, 475 Dhrystone MIPS (estimated);
worst case: 270 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. , 375 Dhrystone MIPS (estimated)
-- Power consumption: 0.35-0.45 mW/MHz (core only)
-- Core size: 1.2-1.5 mm2 (depending on core options)
-- 0-64KB writeback data cache and 0-64KB instruction cache
-- Enhanced JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology.
JTAG - Joint Test Action Group (EJTAG EJTAG Enhanced JTAG (MIPS processors) ) with PC and data trace support for easy debugging
-- Upward compatible with MIPS64(TM)-based cores
-- 5-stage pipeline allows most instructions to execute in one cycle
-- Coprocessor 2 (COP2) interface
The MIPS32 4KE family currently includes the 4KEp(TM) core, which consists of the base configuration; the 4KEm(TM), which features a fast multiplier; and the 4KEc(TM), which features a fast multiplier as well as a memory management unit with a translation lookaside buffer A Translation Lookaside Buffer (TLB) is a CPU cache that is used by memory management hardware to improve the speed of virtual address translation. A TLB has a fixed number of slots containing page table entries, which map virtual addresses onto physical addresses. (TLB TLB - Translation Look-aside Buffer ). All will be available in July as synthesizable or "soft" cores, which can be ported to any silicon process.
Most major operating systems and tool chains, and hundreds of applications, support the MIPS(R) architecture, making it one of the most widely supported of all embedded processor architectures. For the 4KE family, MIPS Technologies is already working with many leading third-party development tool and application vendors for support. For example, the company teamed up with Mentor Graphics Corporation, the leader in hardware/software co-verification, to develop co-verification models for the 4KE family as well as the existing MIPS64 5Kc(TM) and MIPS32 4K(TM) cores. Available from Mentor Graphics, these Seamless(R) co-verification models enable systems developers incorporating the MIPS architecture to validate hardware/software interfaces in a virtual prototype prior to design fabrication fabrication (fab´rikā´shn),
n the construction or making of a restoration. . Mentor Graphics is a member of the MIPS Alliance Program.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and network applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC RISC
in full Reduced Instruction Set Computing
Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
Note to Editors: MIPS(R) is a registered trademark in the U.S. and one or more other countries, and MIPS64(TM), MIPS32(TM), MIPS16e(TM), 4KE(TM), 4KEc(TM), 4KEm(TM), 4KEp(TM), 4K(TM) and 5Kc(TM) are trademarks of MIPS Technologies, Inc. Mentor Graphics and Seamless are registered trademarks of Mentor Graphics Corporation. All other trademarks referred to herein are the property of their respective owners.