MEGACHIPS ADOPTS @HDL SOFTWARE FOR FUCTIONAL VERIFICATION.

@HDL, San Jose, Calif., an emerging leader in design automation for accelerating functional verification, has announced that MegaChips Corporation, one of Japan's leading LSI development companies, has adopted @HDL software for use on System LSI development. MegaChips selected the @Verifier automatic formal verification product and the @Designer graphical debugging product from @HDL after an extensive evaluation. @HDL's products will be used by MegaChips semiconductor engineers developing large scale System on Chip (SoC) designs. Technical support and services for Megachips will be provided by Innotech, the exclusive distributor for @HDL products in Japan.

"It is imperative that MegaChips engineering teams verify the various errors of logic design in the efficient, early design stages for our upcoming strategic large scale LSI projects. We chose @Verifier because of its comprehensive Adaptive Functional Verification (AFV) technology, enabling our designers to verify automatically, without writing property descriptions. Moreover, as a leader in the market, @HDL's support of a unified, assertion-based verification environment based on industry standard assertion languages, will shorten our design and verification cycle," stated Tetsuo Furuichi, Officer of MegaChips Corporation.

"We are honored that MegaChips, with their advanced design and development reputation, has chosen @HDL for their future product development requirements. AFV, our breakthrough technology, offers an environment where engineers can carry out advanced verification, like FSM deadlock detection and multiple clock domain analysis, without complex property creation. @Designer's powerful design analysis functions in the GUI environment greatly mitigate a designer's debugging burden. Moreover, our unique support of both OpenVera and Sugar assertion languages, allows the MegaChips engineering team to immediately improve their verification productivity," stated Badruddin Agarwala, @HDL president and CEO.

@Verifier Features

@Verifier automatically extracts properties from RTL designs to uncover such problems as multiple clock domain synchronization errors, Finite State Machine (FSM) deadlock, and code reach-ability errors. In addition to detecting these tough problems, the automatic property extraction can find an extensive set of other bugs, including one-hot drivers and decoders, parallel and full case statements, unreachable and terminal state, never reachable conditions and codes, FIFO read/write and reset errors, index-out-of range, and stuck at zero/one. In addition, designers can write their system-level assertions and properties using either OpenVera Assertions or Accellera Sugar Assertions. These assertions are then run through the formal model checking engines incorporated in @Verifier. The @Verifier-DP product, offering automatic, distributed processing for model checking, delivers even further productivity gains by running the assertions on different machines or processors in parallel. The overall model checking run times can therefore be reduced by almost a linear rate.

@Designer Features

@Designer delivers a next generation graphical debugging and design analysis environment to quickly isolate functional errors during creation, formal model checking, and simulation of Verilog-based designs. @Designer includes powerful new features not currently provided in other commercially available debuggers including execution tracing, multiple clock domain analysis and visualization, memory content tracing, and source code/memory breakpoints in post-processing mode. Powerful debugging features have been added to allow a unified assertion-based verification environment for OpenVera Assertions and Accellera Sugar Assertions, with support for analysis of both simulation and model checking. Extensive capabilities for debugging RTL, test benches and assertions are now available for use by the MegaChips design and verification personnel.

About Megachips

Established in 1990 as Japan's only research-driven, fabless high-tech company and publicly traded in the Japanese OTC since 1998, MegaChips Corporation, based in Osaka, Japan, develops and manufactures imaging LSIs and systems for consumer video devices and industrial equipment. MegaChips has achieved consistently strong growth by designing, developing and marketing innovative system LSIs and system products, while integrating systems knowledge and semiconductor technology into the core domains of image, sound, voice and network communications. For more information, visit the company website, at www.megachips.co.jp.

About @HDL

@HDL is a privately-held electronic design automation (EDA) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier and @Designer products deliver significant verification productivity improvement for it's customers, including such companies as AMD, OKI Semiconductor, and Toshiba, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. @HDL is committed to supporting the evolving standardization efforts in the area of assertion-based functional verification. With support of industry standard assertion languages, including OpenVera Assertions and Accellera Sugar language, @HDL enables design teams to reap immediate productivity gains in their System-on-Chip (SoC) verification. @HDL is a member of the Cadence (NYSE:CDN) Connections Program and the Synopsys (Nasdaq:SNPS) in-Sync Program.

For more information, call 408/441-1317 or visit http://www.atHDL.com.