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Magma(r) Design Automation Inc. (Nasdaq:LAVA), San Jose San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif., a provider of chip design software, has announced the release of Talus talus (tā`ləs), deposit of rock fragments detached from cliffs or mountain slopes by weathering and piled up at their bases. A talus is a common geologic feature in regions of high cliffs. (r) 1.1, a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs. Talus 1.1 utilizes the new Talus(r) COre(tm) technology, which leverages Magma's unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability. This greatly enhances designers' ability to achieve optimal results across a wide variety of designs -- while minimizing the need for user intervention. Unlike existing routing systems that perform optimization sequentially before and after place and route, and which focus only on layout-oriented routing factors such as design for manufacturability (DFM DFM Design for Manufacturing (newsletter)
DFM Design for Manufacturability
DFM Dubai Financial Market
DFM Delphi Form (computer filename extension)
DFM Distinguished Flying Medal
DFM Diesel Fuel Marine
) or design rule checking (DRC DRC Democratic Republic of Congo
DRC Down (Stage) Right Center
DRC Director(ate) of Reserve Components
DRC Disability Rights Commission (United Kingdom) 
), Talus focuses concurrently on timing and layout-driven metrics during routing.

In addition to its ability to provide the fastest turnaround on large designs, Talus 1.1 introduces the Talus(r) Flow Manager(tm) with "out-of-the-box" design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design -- engineers can easily tune the reference flows for specific applications. Talus Flow Manager also introduces a new visual analysis environment, Talus(r) Visual Volcano(tm), that integrates and presents all design and analysis data via a common display.

"For engineers creating ICs at advanced geometries, big chips, or chips where power management is important, Talus is superior to design systems from other EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  vendors," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "The first breakthrough at Magma occurred when we added concurrent optimization to placement in our initial product, Blast Fusion. Our new Talus COre technology raises the bar by adding concurrent optimization to routing, resulting in faster design closure and better timing performance. Unlike other approaches, Talus delivers a level of design speed and efficiency that is ideal for small-geometry designs -- this also makes it ideal for designers creating big chips, those with 5 million gates or more. This will take on greater commercial significance for our customers as an increased portion of their designs target applications such as netbooks, smartphones and embedded Inserted into. See embedded system.  devices that require bigger and more complex chips but also must be designed for low power."

Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nm, and is presently ready for designs at 32 nm and 28 nm. Such technology is commonly found in System-on-a-Chip (SoC) designs, which integrate computing capabilities on a single chip.

Talus COre Technology

The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk (1) Electromagnetic interference that comes from an adjacent wire. "Alien" crosstalk is interference that comes from a wire in an adjacent cable, for example, when two or more twisted wire pair cables are bundled together.  can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal Suboptimal
A solution is called suboptimal if a part of the solution has been optimized without regards to the overall objective.
 solution with unpredictable results. Traditional solutions must spend time optimizing the design after routing to get the necessary accuracy, but at the cost of long runtimes. Talus COre focuses on applying the full scope of timing optimization incrementally during routing. Every aspect of the routing algorithms -- from topology generation to layer assignment, track assignment and DRC cleanup -- is timing and crosstalk aware. This allows the design to converge faster and eliminate post-route timing surprises. Talus COre is coupled with Talus' SDF-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.

The addition of the Talus COre technology allows Talus 1.1 to deliver optimal quality of results out of the box on advanced process node design challenges. It has already been used to complete production designs where it provided a better than 5 times runtime improvement over competitive solutions and previous Talus versions. In customer beta testing (programming) beta testing - Testing a pre-release (potentially unreliable) version of a piece of software by making it available to selected users. This term derives from early 1960s terminology for product cycle checkpoints, first used at IBM but later standard throughout the  on 40-nm designs ranging from 2 million to 4 million gates, with frequencies from 400 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc.  to 800 MHz, Talus 1.1 produced 75 percent better timing with 10 percent fewer vias than the competitive results.

Talus Flow Manager and Visual Volcano

Talus 1.1 also introduces the new Talus Flow Manager that provides an out-of-the-box Talus RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications. Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC MMMC Maui Memorial Medical Center
MMMC Melaka Manipal Medical College
MMMC Multi-Mode/Multi-Corner
MMMC Miami Maintenance Management Council
MMMC Medical Materiel Management Center
MMMC Modified Modular Mission Computer
MMMC Micky Maus Mini-Comic
) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.

The Talus Flow Manager includes the new Talus Visual Volcano, a new technology designed to help designers make better decisions faster. The Talus Visual Volcano analysis environment offers an integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power and area. MMMC design management is made easier by simplifying the control over active versus reported scenarios, and displaying results for all scenarios concurrently. By consolidating this data into charts and graphs, the Talus Visual Volcano saves time and improves efficiency by removing the need for tedious analysis of log files and textual reports.

About Magma

Magma's electronic design automation (EDA) software is used to create complex, high-performance integrated circuits Integrated circuits

Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1.
 (ICs) for cellular telephones, electronic games Electronic Games was the first video game magazine published in the United States and ran from 1981 to 1985. Co-founded by Arnie Katz, Joyce Worley and Bill Kunkel, it is unrelated to the subsequent Electronic Gaming Monthly. , WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma products for IC implementation, analog/mixed-signal design, analysis, physical verification Physical verification

A procedure auditors use to ensure that inventory recorded in the book is correct by actually checking out the physical inventory.
, circuit simulation and characterization are recognized as embodying the best in semiconductor technology, providing the world's top chip companies the "Fastest Path to Silicon."(tm) Magma maintains headquarters in San Jose, Calif., and offices throughout North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. , Europe, Japan, Asia and India. Magma's stock trades on Nasdaq under the ticker symbol Ticker Symbol

An arrangement of characters (usually letters) representing a particular security listed on an exchange or otherwise traded publicly. When a company issues securities to the public marketplace, it selects an available ticker symbol for its securities which investors

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Publication:Electro Manufacturing
Date:Jul 1, 2009

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