M2000 Unveils Optimized eFPGA Architecture for DSP Functions.MUNICH, Germany -- M2000, an innovator in intellectual property for reconfigurable semiconductors, today unveiled a new architecture for the FlexEOS range of embedded FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. (eFPGA) macros. The new architecture, FlexEOS-DSP, has been optimized to maximize the performance and to minimize silicon utilization when implementing digital signal processing See DSP. Digital Signal Processing - (DSP) Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form (sampled). (DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive ) applications. ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designers now have an efficient means to add in-silicon reconfigurability to applications ranging from image processing to wireless and radar. The new architecture further expands the innovative, silicon-proven FlexEOS solution. It combines reprogrammable logic elements with hard-wired functions that are common in most DSP functions, such as memory blocks, multipliers, accumulators, adders and subtractors. "We believe that the addition of these functions constitutes a very attractive proposition for designers who need to combine DSP calculating power with the flexibility of a reprogrammable core," said Gabriele Pulini, M2000's vice president for marketing. "We have already seen a high level of interest for FlexEOS products in the communications sector, and we are convinced that these additions will be the key for expanding the use of FPGA cores in consumer products such as home digital devices." About FlexEOS-DSP The FlexEOS range of embedded FPGA cores are SRAM See static RAM. SRAM - static random-access memory based, and can be dynamically reconfigured to change the functionality of ASIC and SoC circuits after silicon processing and packaging. FlexEOS macros are currently characterized and manufactured in 90 nanometer CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. technology. The silicon density for logic functions is up to 1,350 LUT's per mm2, and the delay for a LUT (LookUp Table) An array or matrix of values that contains data that is searched. See index and color palette. plus its interconnect is 0.37 ns. The optional DSP-dedicated blocks offer a variety of operating modes: signed/unsigned multiplication, multiply-accumulation, multiply-addition and multiply-subtraction, together with configurable rounding and saturation for performance, which is also enhanced with pipeline registers. The memory blocks can be configured as 4, 8 or 16 bits, and have dual ports, which can be configured independently. For example, a 96K LUT FlexEOS-DSP macro in 90nm contains 768, 500MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. MACs and 3.4Mb of memory blocks. Each macro is delivered with a comprehensive software tool suite for the compilation of the applications which are to run on the macro. FlexEOS macros are suitable for a wide range of applications, and can be supplied for any silicon foundry technology. Availability and Pricing M2000's range of generic FlexEOS products is available for production in 90nm. Evaluation versions of the software are available from M2000. FlexEOS-DSP macros optimized for DSP functions will be available in Q2 2005. The comprehensive pricing structure, which can be tailored to individual requirements, includes a license fee for each project, and royalties on production chips. About M2000 M2000 was created in 1996 by three EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. and FPGA veterans. The founding team has more than 17 years in design of innovative FPGA architectures, and holds numerous patents in the field of configurable logic and its applications for electronic system validation. M2000's current focus is the design and development of state of the art configurable logic technology for the rapidly growing reconfigurable SoC (System on a Chip) market. Corporate headquarters are located at: 1 Route de Gisy, Parc Burospace, Hall 1bis, Bievres, (91570) France. North American North American named after North America. North American blastomycosis see North American blastomycosis. North American cattle tick see boophilusannulatus. headquarters are at: 1095 E. Duane Ave. Suite 203, Sunnyvale, Calif. 94085. Website: http://www.m2000.com Email: info@m2000.fr. |
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