Lucent Technologies Offers New ATM and PCI Software Cores for Field-Programmable Gate Array -FPGA- Chips.ALLENTOWN, Pa.--(BUSINESS WIRE)--Aug. 18, 1998--Lucent Technologies' Microelectronics Group today announced availability of two new ATM software cores for its ORCA Orca - Vrije Universiteit, Amsterdam, 1986. Similar to Modula-2, but with support for distributed programming using shared data objects, like Linda. A 'graph' data type removes the need for pointers. Version for the Amoeba OS, comes with Amoeba. (r) field-programmable gate arrays (FPGAs) and updates to three other ATM and PCI (1) (Payment Card Industry) See PCI DSS.
(2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). cores that the company introduced last year.
Called Customer Solution Cores (CSCs), these pre-coded, pre-tested, and pre-verified building blocks let manufacturers of data communications data communications, application of telecommunications technology to the problem of transmitting data, especially to, from, or between computers. In popular usage, it is said that data communications make it possible for one computer to "talk" with another. and telecommunications network A telecommunications network is a of telecommunications links and nodes arranged so that messages may be passed from one part of the network to another over multiple links and through various nodes. equipment incorporate ATM and PCI functions into their specific designs. The cores provide a wider choice of features, such as different interfaces and control logic, than are available in standard, off-the-shelf chips. They also offer faster FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. design cycles for improved time to market, design flexibility using built-in interface and function options, and source code for easy design integration and modification.
Newly offered are two ATM available bit rate (ABR (1) (AutoBaud Rate detect) The analysis of the first characters of a message to determine its transmission speed and number of start and stop bits.
(2) (Available Bit R ) CSCs from Modelware: the ABR resource management (RM) cell processor, and the ABR RM cell manager. These cores work in conjunction with Lucent's ATLANTA(tm) ATM-switch chip set to provide resource management cell relative rate and explicit rate marking according to according to
1. As stated or indicated by; on the authority of: according to historians.
2. In keeping with: according to instructions.
3. the Bell Laboratories Dynamic Maximum Rate Control Algorithm (DMRCA) or a user-provided proprietary algorithm.
Updates to Modelware's ATM UTOPIA I/II Slave and ATM UTOPIA I/II Master CSCs for ORCA FPGAs increase operating speed from 33 megahertz One million cycles per second. See MHz.
MegaHertz - (MHz) Millions of cycles per second. The unit of frequency used to measure the clock rate of modern digital logic, including microprocessors. (MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. ) to 50 MHz. Updates to Lucent's PCI Master CSC demonstrate 50 MHz performance, add new pinouts The description and purpose of each pin in a multiline connector. for compatibility with Lucent's new OR3TP12 66 MHz embedded-core PCI field-programmable system chip (FPSC FPSC Florida Public Service Commission
FPSC Financial Planners Standards Council (Canada)
FPSC Field Programmable System Chip (Lucent Technologies)
FPSC Fundación Promoción Social de la Cultura ), and upgrade the CSC for use with the most recent releases of synthesis and ORCA Foundry software. In addition, Modelware continues to offer its ATM physical layer CSC for ORCA FPGAs and Lucent continues to offer its PCI Target CSC for ORCA FPGAs.
"With these additions and updates to our CSC product line, we make it easier for communications systems designers to put the latest capabilities into their products in a timely manner," said Barry Britton, Lucent's strategic marketing and product planning director for FPGAs. "We also offer equipment manufacturers the best value by including a complete design solution with source code packaged at a price that's lower than what many vendors charge for their fixed macros without source code."
The new Customer Solution Cores and updates are the latest in Lucent's versatile line of field-programmable IC offerings. In May, Lucent announced its field-programmable system chip, a device that combines mask-programmed standard-cell logic and field-programmable gate array logic on a single slice of silicon. Lucent's FPSCs, which begin shipping next month, offer the component density, high performance and increased functionality of standard-cell logic with the advantages of programmability for faster development and timely delivery of new system features.
All CSCs support 2C/TxxA ORCA devices and third-party simulation and synthesis tools. The CSCs come with a complete design solution package that includes VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. source code and test bench (Verilog for PCI Master CSC); scripts and data files for simulation, synthesis and FPGA layout; and detailed documentation.
The new and updated Customer Solution Cores are available now. The ATM Customer Solution Cores are available directly from Modelware. PCI CSCs are available from Lucent Technologies. Pricing for U.S. customers is as follows:
ATM UTOPIA I/II slave - $8,000 ATM UTOPIA I/II master - $11,000 ATM ABR RM cell manager - $30,000 ATM ABR RM cell processor - $50,000 ATM physical layer - $30,000 PCI master - $7,995 PCI target - $4,495
For product literature, customers may call the Lucent Technologies Customer Response Center Microelectronics, at 1-800- 372-2447, Dept. R41 (in Canada, 1-800-553-2448, Dept. R41); fax number 1-610-712-4106 (especially for callers outside of North America); or write to Lucent Technologies, Room 30L-15P, 555 Union Blvd., Allentown, Pa. 18103. Product literature is also available on the web at http://www.lucent.com/orca.
For further information about the ATM CSCs, customers may also contact Modelware directly at 1-732-389-1922; fax number 1- 732-389-2735; or write to Modelware, 18 Polo Club Drive, Suite 24, Tinton Falls, N.J. 07724. Modelware provides advanced synthesizable cores and design services to the telecom industry. Product literature and other information on the company is available on the web at http://www.modelware.com.
Lucent Technologies designs, builds and delivers a wide range of public and private networks, communications systems and software, data networking systems, business telephone systems and microelectronics components. Bell Laboratories is the research and development arm for the company. For more information on Lucent Technologies, headquartered in Murray Hill, N.J., USA, visit its web site at http://www.lucent.com.
Lucent's Microelectronics Group designs and manufactures integrated circuits and optoelectronic components for the computer and communications industries. More information about the Microelectronics Group is available from its web site at http://www.lucent.com/micro.
Additional Technical Information
The ATM UTOPIA Master CSC implements the ATM Forum's UTOPIA Level 1 and Level 2 specifications. The CSC interfaces to the application (e.g. ATM physical or adaptation layer via a generic FIFO-like access interface, and to multiple physical layer ports via a UTOPIA Level 1 or Level 2 interface. The CSC monitors, in a round-robin fashion, a programmable range of PHY See physical layer and physical. ports and reports their cell-available status to the ATM layer. The ATM layer issues a command to the UTOPIA Master CSC to select a PHY port and initiate cell transfer to that port.
The ATM UTOPIA Slave CSC features Level 1 and Level 2 parity generation and checking, multi-PHY mode support, and 25-MHz, 33- MHz or 50-MHz operation. Both cores feature FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods.
FIFO - first-in first-out control and monitoring, and can use either 128 x 9 internal ORCA FIFOs or external 9-bit IDT IDT Integrated Device Technology, Inc. (Santa Clara, CA, USA)
IDT I Don't Think
IDT Identity Theft
IDT Interrupt Descriptor Table
IDT Integrated DNA Technologies
IDT Inactive Duty Training
IDT Instructional Design & Technology 722x1-type FIFOs. The standalone UTOPIA core can also operate with 16-bit datapaths and thus can use 64 x 17 internal ORCA FIFOs or 18-bit IDT7221x1-type FIFOs. The ATM physical layer core can be implemented in an OR2C/2T15A with external FIFOs or an OR2C/2T26A with internal FIFOs, and the standalone UTOPIA core can be implemented in an ORC2C/2T08A with external or internal FIFOs.
The ABR Resource Management (RM) Cell Processor (RMCP RMCP Remote Mail Checking Protocol
RMCP Remote Management and Control Protocol (Distributed Management Task Force)
RMCP Relayed MultiCast Protocol
RMCP Remote Media Control Protocol
RMCP Reserve Market Clearing Prices ) operates in conjunction with the Lucent Technologies ATM layer Manager (ALM) and ATM Buffer Manager (ABM ABM: see guided missile.
ABM - Asynchronous Balanced Mode ) to provide a complete solution for ABR switch processing in compliance with the ATM Forum's Traffic Management 4.0 specification. The RMCP implements Bell Labs' Dynamic Maximum Rate Control Algorithm (DMRCA) for ABR. The ABR Resource Management (RM) Cell Manager (RMCM RMCM Royal Manchester College of Music (now Royal Northern College of Music; UK)
RMCM Return Material Credit Memorandum (government buy system)
RMCM Radioman, Master Chief ) CSC provides a framework for a user-provided RM cell-marking algorithm instead of the DMRCA algorithm to perform the ABR function.
The ORCA PCI Master/Target CSC provides a complete implementation of a 33 MHz, 32-bit Master/Target interface, compliant to the PCI V2.1 Local Bus Specification. The package includes bidirectional The ability to move, transfer or transmit in both directions. buffering on the master bus, and both the master and target interfaces support full-burst, no-wait-state performance when both sourcing and receiving data. Many other features are supported, such as dual-address, 3.3V and 5V signaling and several optional configuration registers. Complete Verilog source code is supplied, as are test benches and scripts to automate the design process through Synopsys and Exemplar design flows. Also included is a sample design demonstrating ORCA's ability to implement a 50 MHz PCI full-featured solution. Documentation included makes it easy to merge the unit into the final system on an FPGA.
CONTACT: Carl Blesch