LogicVision and Virage Logic Partner to Establish IP Interfaces; Test Chip Validates Interoperability.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 3, 2001

LogicVision, Inc. (Nasdaq:LGVN), a leading provider of embedded test IP for integrated circuits and systems, and Virage Logic (Nasdaq:VIRL), a leader in embedded memory IP, today disclosed a joint development effort to provide interoperability between Virage Logic's Self-Test and Repair (STAR) Memory System (SMS) and LogicVision's embedded test infrastructure. The first phase of the engagement consists of integrating the cores from both companies into a test design and to determine areas in the design flow that could benefit from further automation.

Announced publicly last July, the STAR Memory System (SMS) is the industry's first complete memory system that embeds its own test and repair and the first commercial IP product to support the emerging IEEE P1500 standard for IP test interoperability. The Virage Logic STAR Memory System includes Built-in Self-Test, on-chip Redundancy Allocation and Self Repair. Both companies have co-designed a test chip, as proof on TSMC's 0.13-micron Generic Logic Process. Samples of the test chip are expected to be available for customer evaluation during February 2002. A detailed silicon report is expected to be available in March 2002. In the design, the SMS core is controlled by an IEEE P1500-compliant test port, which interfaces with LogicVision's IEEE 1149.1 test access port (TAP). In addition, the IEEE P1500 wrapper around the STAR Memory System can be controlled from LogicVision's Logic BIST IP to enable testing of the surrounding logic to improve fault coverage. The test chip is expected to be available as part of an evaluation kit including a PC board, USB interface, documentation and software in April 2002.

In addition, both companies have been working with numerous customers to aid the rapid integration of their products into the existing design flow. An application note that outlines what the designer must do to incorporate the Star Memory System and the LogicVision embedded test IP into a design is planned for release in January 2002.

"We believe that Virage Logic's STAR Memory modules provide customers with a robust solution for test and repair, leading to large cost savings through significant improvement in the number of good die per wafer," said Steve Baird, director of business development for LogicVision. "We are working to develop a clean interface from our embedded test infrastructure to the IEEE P1500 ports of the STAR Memory System."

"The interface from our STAR Memory System to LogicVision's TAP and other test infrastructure simplifies the test development work for our customers," said Vincent Ratford, vice president of marketing and business development for Virage Logic. "A significant percentage of SoC designs today contain several million bits of RAM and should use repair to improve die yields. Smaller RAMs can be tested with LogicVision's memory BIST while RAMs with redundancy can be incorporated as part of our STAR Memory System today, with the LogicVision TAP acting as the test manager."

About LogicVision Inc.

LogicVision (Nasdaq:LGVN), provides proprietary technologies for embedded tests that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

About Virage Logic

Virage Logic (Nasdaq:VIRL), is a global technology and market leader in embedded memory. To meet customer design goals with the highest level of quality, Virage Logic products are silicon proven and production ready, and optimized for area, power and speed. These products include embedded memory cores, which are critical components of communications, consumer and computer products including switches, routers, modems, cellular phones, set-top boxes, HDTVs, DVD players and PCs. In addition, the company offers software tools and custom memory design services. The company's customers include fabless semiconductor companies who use pure-play foundries and other semiconductor companies. Founded in January 1996, the company has over 180 employees and is located at 46501 Landing Pkwy., Fremont, Calif., 94538. Telephone: [phone] (toll free) or 510/360-8000. Fax: [phone]. For more information, please visit www.viragelogic.com.

ACRONYMS AND DEFINITIONS:

ATE:     Automatic Test Equipment
ATPG:    Automatic Test Pattern Generation
BIST:    Built-in-Self-Test
DFT:     Design-for-Test
EDA:     Electronic Design Automation
GDSII:   An industry format describing the physical structure of the
         chip design and used to create mask tooling for chip
         manufacturing.
GUI:     Graphics User Interface
HDL:     Hardware Description Language -- Describes the architecture
         and behavior of discrete electronic systems.
IC:      Integrated Circuit
RTL:     Register Transfer-Level -- A chip design language format --
         technology independent that can be Verilog or VHDL.
Verilog: A hardware description language used to design and document
         electronic systems.
VHDL:    VHSIC (Very High-Speed Integrated Circuit) HDL
IP:      Intellectual Property
SoC:     System-on-chip

FORWARD LOOKING STATEMENTS:

Except for the historical information contained herein, the matters set forth in this press release, including statements as to the development efforts, the expected availability of samples of the test chip, a detailed silicon report, evaluation kit and application note, and the expected benefits of the STAR Memory modules, including cost savings and improvement in the number of good die per wafer, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the ability of the companies to integrate their technologies in the joint development effort, the impact of competitive products and pricing and of alternative technological advances, and other risks detailed in LogicVision's Prospectus dated October 31, 2001 filed with the SEC and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

Note to Editors: LogicVision, Embedded Test, LogicVision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.