LogicVision Unveils Run-Time Programmable Embedded Test for Memories.

Business Editors and High Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--June 11, 2001

Programmable Memory BIST First to Enable Customer Defined Algorithms

to be Applied to Screen Defects After Chips, Boards and

Systems are Manufactured

LogicVision, Inc., a leading provider of embedded test IP solutions, introduces Programmable Memory BIST. This product can be used for characterization, manufacturing diagnosis, and manufacturing production test of ICs incorporating large, embedded memories. The product enables user-defined memory algorithms to be loaded into the embedded test controller at run time, or stored on-chip as defaults. The controller can apply any number of unique algorithms at application speed. Programmable Memory BIST supports one or more embedded DRAMs or embedded SRAMs and handles a range of memory timing protocols including SDRAM, EDO and Page Mode.

"With our drive towards aggressive feature sizes for advanced embedded RAM designs, it was not possible to model failures, nor to predict failures in the design stage. The Programmable Memory BIST product gave us the flexibility to alter our test algorithms at run-time to accommodate any new understanding in advanced VDSM process failure modes. As with other LogicVision embedded test products, Programmable Memory BIST can be re-used by our system, and manufacturing divisions to increase their level of testability of systems comprised of the devices using advanced RAMs with the Programmable Memory BIST", says Mitsuyasu Ohta, Manager, EDA Technology Development Group, System LSI Technologies Coordination Department, Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

LogicVision Vice President of Marketing and Business Development Rodger Sykes, stated, "LogicVision's Programmable Memory BIST solves advanced testing issues that arise as ever-larger memories and ever-shrinking geometries create uncharacterized failure modes. For the first time, SOC customers can create and deploy unique and optimized algorithms to screen for defects to screen for defects at diagnosis and during volume manufacturing."

These enhanced IC design and test advances are scheduled to be demonstrated at the Design Automation Conference (DAC) in Las Vegas, NV, June 18-21, both at LogicVision's DAC Exhibit Booth No. 3633, as well as LogicVision's Demo Suite No. 7134.

About LogicVision Inc.

LogicVision provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

ACRONYMS AND DEFINITIONS:
APG: Algorithmic Pattern Generation
ATE: Automatic Test Equipment
ATPG: Automatic Test Pattern Generation
BIST: Built-in-Self-Test
DFT: Design-for-Test
EDA: Electronic Design Automation
HDL: Hardware Description Language  IC: Integrated Circuit
RTL: Register Transfer-Level
VDSM: Very Deep Sub-Micron
VHDL: VHSIC (Very High-Speed Integrated Circuit) HDL
IP: Intellectual Property
SOC: System-on-chip