Loading effects on transmission lines, part 1: device loading can influence critical transmission line characteristics, and the design of high-speed PCBs.

WHEN DEVICES SUCH as ICs are connected to high-speed PCB traces, their inductance and capacitance add to that trace's inductance and capacitance, thus loading down the line (1). This loading effect can alter certain transmission line properties, such as characteristic impedance (Zo) and propagation delay (Tpd), and hence influence the board design.

Let us first consider Zo and Tpd formulas for two commonly occurring PCB trace geometries (2), microstrip and stripline, when loading effects are negligible (i.e., unloaded line) as in Table 1. Equation 1, relating to characteristic impedance (3,4) Zo of microstrip, is IPC recommended (4).

FIGURE 1 demonstrates the Zo of an unloaded microstrip vs. trace width (W) for four different values of trace height (substrate thickness) based on Equation 1. It is recommended (5) that the results of Equation 1 be utilized only for conditions involving narrow microstrip (i.e., when 0.1<W/H<2.0). Formulas for microstrip Zo suitable for skinny traces (W<H) and wide traces (W>H) are discussed by Howard Johnson et al. (5).

[FIGURE 1 OMITTED]

This plot assumes a relative dielectric constant Er = 4.25 for an FR-4 substrate. It utilizes a fixed trace thickness of .00141" (1 oz copper weight), and ignores effects due to soldermask. The impact of trace thickness variations on impedance is relatively small (6)--about 1 ohm per .001" (a thicker line produces smaller Zo).

The effect of soldermask on microstrip Zo can also be easily estimated. Zo decreases by approximately 1 ohm/0.001" of soldermask thickness (6). The influence of W, H and Er upon Zo are regarded as first order factors, whereas T and soldermask possess second order effects (6) on characteristic impedance.

For stripline, impedance formulas (3,4) include Equations 3 and 4 (approximately equivalent). The latter formula (4) is IPC recommended. Generally, formulas in TABLE 1 are approximations with higher accuracies achievable using field solvers.

FIGURE 2, based on Equation 4, shows unloaded characteristic impedance of a symmetric stripline (trace equidistant from two planes) as a function of trace width for four values (B) of plane-to-plane spacing.

[FIGURE 2 OMITTED]

For Figure 2, it is assumed that Er = 4.25, and T = .00141". The Zo formulas (Equations 1, 3 and 4) reveal that the physical dimensions appear as arguments to a natural logarithm (log to base e=2.7182818 as opposed to common log having a base 10) function. Subsequently, impedance varies slowly as a function of trace geometry. This indicates that large changes in physical dimensions cause a small impact (5) on impedance. This is desirable and implies that impedance is not very sensitive to physical dimensions. (Impedance sensitivity5 is the percent change in impedance per percent change in line width as revealed by the slope of the impedance function on a log-log plot.)

The microstrip propagation delay expression (3) in Equation 2 assumes that effective dielectric coefficient Er_eff (= 0.475Er + 0.67) is a constant, which is an approximation, since the microstrip propagation time can vary (7,8) with trace width and height above the ground.

The Tpd formulas for outer and inner layers (Equations 2 and 5, plotted in FIGURE 3) vary only with substrate dielectric constant, and indicate independence from physical trace dimensions within the first order approximations.

[FIGURE 3 OMITTED]

Applying these formulas to FR-4 whose nominal Er = 4.25 (FR-4 Er can range (4) from approximately 4.0 to 4.5) will yield a Tpd of ~ 1.67 nsec/ft and ~ 2.09 nsec/ft for microstrip and stripline, respectively.

In Figure 3, the unit of propagation delay is nsec/ft. Another common unit for Tpd is psec/in. Since 1 nsec = 1000 psec and 1in = 1/12 ft, values in nsec/ft can be multiplied by 83.33 (1000/12) to convert to psec/in.

Conversely, psec/in is translated to nsec/ft by dividing by 83.333 or multiplying by 0.012 (1/83.333).

The first example treats such unit conversions.

Example 1. Converting 1.67 nsec/ft to its equivalent in psec/in requires multiplication by 83.333.

Hence, 1.67 nsec/ft = 139.17 psec/in. Translation of 180 psec/in to nsec/ft is achieved by multiplying by 0.012, which yields 2.16 nsec/ft.

The Tpd for microstrip is smaller than the Tpd for stripline, because the signal velocity (V) on outer layers is faster than V on inner layers, with Tpd and V being inversely related. One implication of this concept is described by the next example.

Example 2. Layout solution space analyses (9,10) often necessitate determining the minimum and maximum lengths for high-speed nets. Because trace velocity is faster for microstrip (than stripline), the traces on outer layers can be longer (as compared to inner layer routing), which is frequently easier to route. For instance, in one application it was ascertained by simulations that the maximum allowable high-speed trace length could be 5" when routed as stripline but 5.5" if routed as microstrip.

TABLE 1. The characteristic impedance and propagation delay values for
(unloaded) microstrip and symmentric stripline are shown.

Parameter                 Formula              Unit     PCB Geometry

Characteristic    Zo = 87/[square root of     [OMEGA]   [ILLUSTRATION
Impedance         Er+1.41] x {ln[5.98h /                  OMITTED]
(Microstrip)             (0.8W+T)]}
                        (Equation 1)

Propagation      Tpd = 1.017[square root of    nS/ft    [ILLUSTRATION
Delay                 0.475Er + 0.67]                     OMITTED]
(Microstrip)            (Equation 2)

Characteristic     Zo = (60/[square root      [OMEGA]   [ILLUSTRATION
Impedance           of Er]) x {ln[4B /                    OMITTED]
(Stripline)       (0.67[pi]W(0.8+T/W)))]}
                        (Equation 3)

Characteristic     Zo = (60/[square root      [OMEGA]   [ILLUSTRATION
Impedance          of Er]) x {ln[2B + T)                  OMITTED]
(Stripline)            / (0.8+T/W))]}
                        (Equation 4)

Propagation         Tpd = 1.017[square         nS/ft    [ILLUSTRATION
Delay                   root of Er]                       OMITTED]
(Stripline)             (Equation 5)

Er is a relative dielectric constant of the substrate material.
W is trace width. H is height of microstrip relative to reference
power/ground plane (i.e., dielectric substrate thickness). T is
thickness of trace. B is separation of the two plan layers (for
the symmetric stripline configuration).

Ed. Part II will be published in the next installment of Interconnect Strategies.

ACKNOWLEDGEMENTS

The author would like to thank Peter Arnold for reviewing the manuscript, and Jeremy Plunkett and Dean Gonzales for their helpful discussions.

REFERENCES

(1.) Transmission Line Effects In PCB Applications, Motorola Semiconductor Application Note AN1051/D, 1990, P. 10, PP. A-1 to A-4.

(2.) Abe Riazi, "Engineer's Rule of Thumb Simplifies PCB Signal Integrity," EEdesign, August 19, 2002.

(3.) James K. Hollomon, Jr., "Surface Mount Technology for PC Board Design" Howard W. Sams & Co., 1989. PP. 180-182.

(4.) Eric Bogatin, "Signal Integrity Simplified," Prentice Hall, 2004, P. 130, P. 260, PP. 320-323.

(5.) Howard Johnson and Martin Graham, "High-Speed Digital Design a Handbook of Black Magic," Prentice Hall, Inc., 1993. P. 181, P. 187, P. 433.

(6.) Eric Bogatin, "When Accuracy Counts," Printed Circuit Design & Manufacture, May 2003, P. 36.

(7.) Douglas Brooks, "Signal Integrity Issues and Printed Circuit Board Design," Prentice Hall. 2003. P. 30, P. 206.

(8.) Douglas Brooks, "Microstrip Propagation Time," Printed Circuit Design & Manufacture, May 2004, PP. 28-29.

(9.) Stephen H. Hall, Garrett W. Hall and James A. McCall, "High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices," John W. Wiley and Sons, Inc. 2000, PP. 212-213.

(10.) Todd Westerhoff, "Solution Space Analysis for High-Speed Design," Printed Circuit Design, August 2000, PP. 16-22.

ABE (ASBAS) RIAZI (ariazi@server works.com) is a senior signal integrity engineer with ServerWorks (a Broadcom company) in Santa Clara, CA.