Loading effects on transmission lines, Part 2: a minimum loaded line impedance may be essential to your design.

Ed.: References for footnotes 1-10, equations 1-5, figures 1-3, and table 1 are found in Part 1 of this column, published in the May issue of PCD&M, available at www. pcdandm.com.

A LOADED LINE may be defined as a transmission line having a distribution of uniformly spaced capacitive loads (4). The characteristic impedance and propagation delay formulas for loaded lines are shown in TABLE 2.

A comparison of equations in Tables 1 and 2 reveals that the loaded or effective characteristics impedance (Zo') and propagation delay (Tpd') are related to the unloaded--also called intrinsic or natural--impedance (Zo) and propagation delay (Tpd) (1, 11) by:

EQUATION 11 Zo' = Zo/[square root of 1+ (Cd/Co)]

EQUATION 12 Tpd' = Tpd x [square root of 1+ (Cd/Co)]

Co is the intrinsic capacitance of the trace and Cd is the distributed capacitance of the receivers, both per unit length. The normalized effective characteristic impedance (12) and propagation delay are given by:

EQUATION 13 Zon = Zo'/Zo = 1/[square root of 1+Cr]

EQUATION 14 Tpdn = Tpd'/Tpd = [square root of 1+Cr]

Where Cr = Cd/Co is a non-negative dimensionless number.

Plots of Zon and Tpdn (also dimensionless) in terms of Cr are shown in FIGURE 4.

[FIGURE 4 OMITTED]

1+Cr (and its square root) is equal to or greater than unity (1 + Cr = 1 corresponds to the case of the unloaded line). Subsequently, EQUATIONS 13 and 14 (also Figure 4) reveal that impedance is decreased and propagation delay is increased (signal velocity is slowed down) due to loading effects.

For instance, Cr = 3.0 results in the doubling of the transmission line propagation delay (i.e., Tpdn = 2.0), and halving the effective characteristic impedance (i.e., Zon = 0.5).

One implication of loading concepts is that in various high-speed PCB termination (11) techniques such as series, parallel, Thevenin, etc., the loaded line characteristic impedance (Zo') should be utilized when computing the optimum values for terminators, not the unloaded (Zo).

Loading effects can also impose the insertion of dummy vias (13) on some nets of a high-speed bus, in order to equalize the loading and delay differences between various lines of the bus by forcing each line to have the same number of dummy and real vias. This can minimize layer-to-layer skew and thus maximize performance of the design.

In some cases a minimum loaded line impedance is essential for maintaining signal quality, such as keeping the first signal plateau beyond receiver threshold. A formula for calculating the maximum load density that sustains the line impedance above the minimum pre-defined value is presented in IPC-D-317 (14).

Such loading effect concepts hold valid for electrically short topologies. Examples 3 and 4 provide further insight regarding applications of loading effects.

Example 3. A topology with several loads uniformly distributed (with negligibly short stub lengths to minimize noise) along a transmission line is shown in FIGURE 5. The transmission line includes four segments: T1, T2, T3 and T4, having length Y.

[FIGURE 5 OMITTED]

Each receiver presents a load capacitance CL. The formulas discussed earlier can be applied to this network.

Assuming each segment has unloaded characteristic impedance (Zo) and propagation delay (Tpd), then:

Co = Tpd / Zo

The distributed capacitance (Cd) is computed from the ratio of total receivers' loading capacitance (4CL) to line length (4Y):

Cd = 4CL/4Y = CL/Y

The corresponding loaded line impedance and delay can then be cal culated via EQUATIONS 11 and 12.

To assert distributed (rather than lumped) effect, the capacitive loads need to be distributed uniformly, and the electrical delay between the neighboring loads should be less than the rise or fall times of the signal. Such loading effectively alters the transmission line's propagation velocity and characteristic impedance.

No terminators are shown for this topology, although termination may be required depending on such factors as the signal rise/fall times, the line length, value of CL, and amount of ringing which can be tolerated on the bus. Loading types are frequently (15, 16) classified as distributed (uniform along a length of line) or lumped (concentrated at a single point). A lumped variation of Figure 5 is depicted in FIGURE 6. All receivers are located at the far end of the line producing a large capacitive load.

[FIGURE 6 OMITTED]

At fast edge rates, the distributed proves superior to the lumped modeling. A numerical specimen is furnished by the final example.

Example 4. Consider a microstrip with unloaded Zo = 60_ and Tpd = 1.8 ns/ft. This indicates intrinsic trace capacitance of Co = Tpd/Zo = 0.030 nF/ft = 30 pF/ft = 2.5 pF/in.

Let trace length = 5 inches with three receiver ICs to be distributed along the line, with zero stub lengths.

Assume a loading of 4.0 pF per device, resulting in total loading of 12 pF, and a driver rise/fall time of 0.7 ns.

Subsequently, Cd = 12pF/5 in = 2.4 pF/in.

The calculated loaded values are: Zo' = 42.86 Ohms and Tpd' = 2.52 ns/ft.

Furthermore, 2 x Tpd' x trace length = 2 x 2.52 ns/ft x 0.417 ft = 2.1 ns.

Since this exceeds the signal's rise or fall times, there may be transmission line effects such as ringing and a need for termination.

ACKNOWLEDGEMENTS

The author would like to thank Peter Arnold for reviewing this column, and Jeremy Plunkett and Dean Gonzales for their helpful discussions.

TABLE 2. The effective impedance and propagation delay for loaded
microstrip and symmetric stripline.

Parameter                             Formula                    Unit

Effective             Zo' = 87 / [square root of                [omega]
Characteristic        (Er+1.41)] x  {In[5.98H / {0.8W+T)]} /
Impedance             [square root of (1+(Cd/Co)]
(Microstrip)                       (Equation 6)

Effective             Tpd' = 1.017 [square root of               ns/ft
Propagation Delay     (0.475Er + 0.67)] x [square root of
(Microstrip)          (1+(Cd/Co))]
                                   (Equation 7)

Effective             Zo' = (60 / [square root of (Er)]) x      [omega]
Characteristic        {In[4B / (0.67[pi]W(0.8+T / W))]} /
Impedance             [square root of (1+(Cd/Co))]
(Stripline)                        (Equation 8)

Effective             Zo' = (60 / [square root of (Er)]) x      [omega]
Characteristic        {In[(2B + T) / (0.8W+T)]} /
Impedance             [square root of (1+(Cd/Co))]
(Stripline)                        (Equation 9)

Effective             Tpd' = (1.017 [square root of (ER)]) x     ns/ft
Propagation Delay     [square root of (1+(Cd/Co))]
(Microstrip)                       (Equation 10)

Er is a relative dielectric constant of the substrate material. W
is trace width. His height of microstrip relative to reference
power/ground plane (i.e., dielectric substrate thickness). T is
thickness of trace. B is separation of the two plane layers
(for the symmetric stripline configuration). Cd is the distributed
capacitance of receivers. Co is a trace's intrinsic capacitance.

REFERENCES

(11.) Karthik Ethirajan and John Nemec, "Termination Techniques for High-speed Buses," EDN, Feb. 16, 1998, PE 135-143.

(12.) Jose M. Soltero, "Design High-Speed Backplanes That Work" Electronic Design (Components & Packaging Vision Supplement), Oct. 29, 2001, PR 12-20.

(13.) Bryce Horine and Mike Leddige, "Using Routing Techniques to Minimize Skew," Printed Circuit Design, December 1999, PP. 24-27.

(14.) "Design Guidelines for Electronic Packaging Utilizing High-speed Techniques," IPCD-317, April 1990, PP. 24-26.

(15.) Sol Rosenstark, "Transmission Lines in Computer Engineering" McGraw Hill, Inc., 1994, PP. 67-85.

(16.) "Understanding and Minimizing Ground Bounce" Fairchild Application Note 640, February 1998.

ABE (ABBAS) RIAZl (ariazi@server works.corn) is a senior signal integrity engineer with ServerWorks (a Broadcom Company) in Santa Clara, CA.