Lexra Announces Industry's First RISC-DSP Core Based On MIPS Instruction Set Architecture; The LX5280 is the First Implementation of the RADIAX DSP Extensions.

SAN JOSE, Calif.--(BUSINESS WIRE)--May 5, 1999--

Lexra, a leading developer of processor cores for embedded applications, announced today at the Embedded Processor Forum the LX5280, the industry's first RISC-DSP core based on the MIPS(R) instruction set architecture.

Offering the ease-of-use of a RISC architecture together with state-of-the-art DSP performance and power efficiency, the LX5280 runs MIPS software and eliminates the need for separate RISC and DSP processors. In a separate announcement today, Lexra announced the RADIAX(TM) DSP extensions, which will be available to MIPS licensees under a royalty-free license agreement.

The LX5280 is delivered as a core, rather than a chip; therefore it offers all of the benefits of the IP business model -- foundry independence and the ability to add co-processors and custom instructions -- while allowing the licensee to tailor memory sizes and peripherals to individual system requirements. In addition, the LX5280 RISC-DSP core can be replicated within a single System-On-Chip (SOC) to provide high performance and low power for multi-channel DSP applications such as remote access concentrators.

"We are pleased to offer the world's first RISC-DSP core based on the MIPS ISA," stated Charlie Cheng, president and CEO of Lexra. "The LX5280 will fuel the development of new products in DSP-intensive applications such as IP telephony, ADSL modems, digital cameras, MP3 players, and other devices that process real-time signals."

The LX5280 uses a dual-issue, seven-stage pipeline, and supports Lexra's RADIAX DSP extensions to the MIPS instruction set. Based on Lexra's high performance 32-bit R3000(R)-class CPU, the LX5280 adds dual 16-bit/32-bit multiply-accumulate (MAC) engines that are pipelined to provide sustained single-cycle 16-bit multiply-accumulate performance. The LX5280 supports MIPS EJTAG in-circuit emulation capability, and MIPS16(R) code compression.

The LX5280 eliminates the need for two separate processors, reducing chip size and system cost. It also eliminates the need for two software development efforts, reducing time-to-market for applications that require both signal processing and general processing.

Development tool and software support for the LX5280 will come from the industry's leading third party MIPS tool suppliers including California Advanced Software Tools, Embedded Performance Inc. and Green Hills Software.

As the electronics and semiconductor market driver shifts from the PC to communications, the market for DSP-intensive products is seeing explosive growth. New products require signal processing for analog, or real-time data, and general computing for control, protocol processing, and other non-signal processing tasks. Examples of such products include ADSL modems, G3 cellular phones and base stations, Voice over IP gateways, digital cameras, MP3 audio players, disk drive controllers, anti-lock braking systems. Key requirements for these products are high performance combined with low power and small die size.

Traditional 16-bit DSP architectures are reaching a performance plateau at 120 - 125 MHz. While new 32-bit VLIW (Very Long Instruction Word) architectures can operate at speeds up to 250 MHz, power consumption is high. Both architectures typically require a separate microcontroller for non-DSP tasks, which results in inefficiencies because the two processors have limited ability to share power and resources such as system memory. Neither traditional 16-bit architectures nor 32-bit VLIW architectures are suited to programming in high-level languages, which results in software that is difficult to create, maintain, and upgrade.

In developing the LX5280 RISC-DSP core, Lexra's goal was to address these key issues. Lexra chose the MIPS architecture for its performance and because it is easy to program, with broad and robust software and development tool support.

"Lexra's superscalar architecture is very well suited to RISC-DSP because it delivers the extra memory bandwidth required by DSP algorithms while preserving the simple RISC execution model," said Pat Hays, vice president and CTO of Lexra. "Compared to new VLIW DSPs, the LX5280 programming model is far simpler. As a result, compiled code as well as customer assembly code, is more efficient."

In 0.18-micron technology, the LX5280 achieves a worst-case system clock speed of 200 MHz, with a peak computational power of 400 million multiply-accumulate (MAC) operations per second, comparable to the highest-performance DSPs available. The die size for the entire LX5280 processor subsystem will be approximately 6 mm-squared, with power consumption of 225mW.

Availability:

The LX5280 RTL core will be available in November of 1999. License fees start at $495,000 plus unit royalty of $1.95 per chip. The RTL core includes the Verilog database, synthesis scripts and a regression suite. The SmoothCore(TM) version of the LX5280 will be available in February of 2000, and will include physical databases for major foundries.

About Lexra:

Lexra, Inc. is a leading microprocessor developer specializing in RISC and DSP cores for the embedded market. In addition to competitive performance, small die size and low power consumption, Lexra's processor cores are also easy to use, easy to port and provide customers with cost effective solutions. Lexra is headquartered in Waltham, Mass. Further information can be found at http://www.lexra.com.

MIPS, MIPS I, MIPS16, R3000, and other MIPS common law marks are trademarks and/or registered trademarks of MIPS Technologies, Inc. Lexra, Inc. is not associated with MIPS Technologies, Inc. in any way. Unaligned loads & stores are not supported in hardware.