Lattice Semiconductor Selects Verific's HDL Component Software.Tool is Integrated into the ispLEVER Software Design Tool Suite ALAMEDA, Calif. -- Verific Design Automation today announced that Lattice Semiconductor Corporation (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : LSCC LSCC Lake-Sumter Community College (Florida) LSCC Lattice Semiconductor Corporation (stock symbol) LSCC Lawson State Community College (Alabama) ) last month selected its hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) Component Software to integrate into Lattice's ispLEVER([R]) 6.1 software design tool suite. Verific's HDL Component Software -- SystemVerilog, Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. parsers, analyzers and elaborators -- is used for exploring, navigating, analyzing, documenting and modifying large FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. designs within the ispLEVER design environment via Lattice's new HDL Explorer[TM] capability. The HDL Explorer tool within the ispLEVER suite integrates design creation, analysis, verification and documentation in a customizable HDL analysis environment. The HDL Explorer tool generates graphic representations of a design's hierarchical structure and connectivity based on the source HDL, and is used for IP integration, design maintenance and re-engineering of complex FPGA HDL designs. The HDL Explorer tool helps designers visualize higher-level abstractions of the design structure, reducing the time required for design management and documentation. The HDL Explorer tool also helps designers produce high-quality code with "linting" technology to detect common design rule faults. Chris Fanning, corporate vice president of software and IP solutions, said: "Verific's HDL Component Software is a comprehensive tool that Lattice has leveraged in its development of our HDL Explorer tool, a significant new capability that enables FPGA designers to more effectively and quickly complete their designs." "Lattice's ispLEVER design tool suite is noted for its ease of use, flexibility and performance," said Rob Dekker, Verific's president. "We're delighted to be part of a tool suite that so effectively serves the programmable logic designer community." Verific's HDL Component Software is written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance. About Lattice Semiconductor Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. ), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. ), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES See serializer/deserializer. products. Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice's ispLEVER 6.1 adds new design resources and productivity enhancement tools for designers, including the innovative HDL Explorer tool that helps manage and analyze large FPGA designs. The ispLEVER 6.1 release supports Lattice's latest FPGAs, including the new LatticeECP2M[TM] FPGA family, the new LatticeMico32[TM] System for 32-bit microprocessor design and enhanced third-party synthesis and simulation tools. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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