Lattice Semiconductor Boosts SuperBIG 3.3V ISP PLDs to 1080 Macrocells.Business Editors HILLSBORO, Ore.--(BUSINESS WIRE)--March 13, 2000 --Lattice's ispLSI(R) 8000V Family Provides the Industry's Largest, Low-Voltage Complex PLDs With up to 1440 registers and internal tristate buses for on-chip microprocessor bus extension-- Lattice Semiconductor Corporation (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : LSCC LSCC Lake-Sumter Community College (Florida) LSCC Lattice Semiconductor Corporation (stock symbol) LSCC Lawson State Community College (Alabama) ) today announced the new ispLSI 8000V family, the 3.3-Volt SuperBIG(TM) line of in-system programmable (ISP (1) See in-system programmable. (2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. (TM)) CPLDs. The new low-voltage devices feature up to 1080 macrocells and up to 360 input/output registers for a total of 1440 registers, making them the largest complex PLDs available. The ispLSI 8000V devices couple very high densities with blazing fast operating frequencies of up to 125MHz and 8.5ns pin-to-pin logic delays (Tpd). The ispLSI 8000V family is based on the company's proprietary E2CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. (R) electrically erasable technology and the advanced architecture of the popular ispLSI 8000 family. With this release, all of Lattice's innovative SuperBIG, SuperFAST(TM) and SuperWIDE(TM) high performance PLDs are available in true 3.3V families, allowing designers to leverage the combined benefits of speed, 68-input wide logic, and high CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. densities for all their low-voltage requirements. "Lattice continues to push CPLD densities with the ispLSI 8000V family while providing a roadmap for lower-voltage system design," said Stan Kopec, Vice President of Corporate Marketing for Lattice Semiconductor. "Even with their impressive densities, the SuperBIG devices provide superior system performance, enabling them to continue to encroach on traditional FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. applications." The new SuperBIG ispLSI 8000V devices deliver high performance with pin-to-pin logic delays (Tpd) to 8.5 ns and an internal operating frequency (Fmax) of 125 MHz. The largest 3.3V device, the ispLSI 81080V contains 360 I/Os. All ispLSI 8000V device I/Os are 5-Volt tolerant and support user selectable 3.3V or 2.5V I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output . Boundary scan test and ispJTAG(TM) in-system programming are supported via the JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group (IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1149.1) test access port. Architecture The new ispLSI 8000V architecture features general-purpose macrocells contained in five, seven or nine Big Fast Megablocks (BFMs), respectively. Each BFM BFM Berlin-Frankfurt-Münster (study group) BFM Bus Functional Model BFM British Furniture Manufacturers (UK) BFM Bonded Fiber Matrix (soil stabilization for erosion control) consists of six, 20-macrocell wide Generic Logic Blocks (GLBs) with 44 inputs per GLB (Gramm-Leach-Bliley Act) Enacted in 1999 and effective in mid 2001, the GLB stipulates that every financial institution shall protect the security and confidentiality of its customers' confidential personal information. . The popular architecture delivers both high-speed Global and Big Fast Megablock interconnects using a unique Global Routing Plane (GRP GRP Group GRP Group (file name extension) GRP Glass Reinforced Plastic GRP Gastrin-Releasing Peptide (biology) GRP Gross Rating Point (advertising) ) architecture. Acting like a programmable silicon backplane, the GRP delivers high-speed 2-ns global interconnect. A second-generation product term sharing array supports up to 28 product terms per macrocell output. The ispLSI 8000V and 8000 SuperBIG devices are the industry's only PLDs to include an embedded tristate bus that can be configured as either twelve 9-bit buses or in combinations up to one 108-bit bus. Built-in bus arbitration logic prevents bus contention to improve performance and eliminate potential logic hazards. The embedded bus can be utilized as an internal bus or an extension of an external tristate bus and is excellent for microprocessor peripheral applications. Applications Lattice's SuperBIG ispLSI 8000V devices, with their wide input logic architecture and internal tri-state buses, are particularly well suited for high speed data processing and communications applications requiring interface with multiple system buses. Fast Programming Times Lattice delivers the fastest programming times in the industry with all its ISP devices featuring on-board programming times of less than five seconds. These fast programming speeds are the result of Lattice's advanced architectures and manufacturing processes. They are supported by the ispVM(TM) System, Lattice's "virtual machine" for programming devices from multiple vendors. Software Support The new ispLSI 8000V family of devices is supported by version 8.0 of Lattice's ispDesignEXPERT(TM) Systems for in-system programmable logic design, including the ispDesignEXPERT Compiler with Viewlogic and the ispDesignEXPERT System with Synplicity. These tools assist system designers in realizing the best implementations of increasingly more complex system-level functions. The third generation ispDesignEXPERT Logic Compiler is specifically designed to optimize VHDL- and Verilog-based logic designs synthesized by third-party HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. synthesis tools for the advanced architectures of Lattice's SuperBIG, SuperFAST and SuperWIDE ISP device families. Lattice's software tools support logic design implementation in all leading CAE (1) (Computer-Aided Engineering) Software that analyzes designs which have been created in the computer or that have been created elsewhere and entered into the computer. environments. Pricing and Availability All family members are available today in the 272-BGA or 492-BGA packages. In a 272 BGA package, the ispLSI 8600V, ispLSI 8840V, and ispLSI 81080V are priced at $41.00, $52.00 and $65.00, respectively, in 1,000 piece quantities. About Lattice Semiconductor Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP(TM) programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs. Lattice introduced in-system programmability to the logic industry in 1992. In June 1999, Lattice acquired Vantis, the corporation that invented the PAL(R) device and PLD switch matrix architecture, from AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. . With nearly double the R&D and sales resources, the resulting integrated company will focus on delivering logic products that satisfy the performance, density and ease-of-use requirements of its customers. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web sites at http://www.latticesemi.com. Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties, including the effect of changing economic conditions, the effect of overall semiconductor market conditions, product demand risks, risks associated with dependencies on silicon wafer suppliers and semiconductor assemblers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. Lattice Semiconductor, L (stylized styl·ize tr.v. styl·ized, styl·iz·ing, styl·iz·es 1. To restrict or make conform to a particular style. 2. To represent conventionally; conventionalize. ) Lattice, ISP, ispJTAG, ispLSI, ispVM, SuperBIG, SuperFAST, SuperWIDE, ispLSI 8000, and ispDesignEXPERT are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. |
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