Lattice Semiconductor Announces Production Release of New Low-Cost FPGA Products; First Low-Cost FPGAs To Support 400Mbps DDR Memory Interfaces Now Shipping.

HILLSBORO, Ore. -- Lattice Semiconductor Corporation (Nasdaq:LSCC) today announced the production release of the first members of its LatticeECP-DSP(TM) (EConomy Plus DSP) and LatticeEC(TM) (EConomy) FPGA device families. Production-tested and qualified, the 20K Look-Up-Table (LUT) ECP20 and EC20 devices are now shipping.

The ECP-DSP20 and EC20 devices feature pre-engineered 400 Mbps DDR memory interfaces, the only low-cost FPGAs in the market to achieve this performance level. The devices can be configured using low-cost, multi-sourced SPI Flash memory. The ECP-DSP20 also features 7 sysDSP(TM) blocks capable of implementing up to twenty-eight 18x18 multipliers with dedicated accumulator and pipelining logic for extra speed and density.

The LatticeECP(TM) and LatticeEC devices are implemented on a cost-effective, production-proven, Low-k, 130nm CMOS process with copper metallization fabricated by Fujitsu Limited. This process technology, combined with efficient silicon design, results in very small die sizes while providing the new Lattice FPGAs with the most attractive feature sets in their class.

Real Products In Real Time

Lattice first described its LatticeECP/EC product families March 23, 2004, and announced the devices in detail June 28, 2004. "We publicly committed to deliver the first samples of the LatticeECP and LatticeEC families to the marketplace in the third quarter, and we made our first customer shipment in August," said Stan Kopec, Lattice vice president of corporate marketing. "We have now moved into full production as a result of excellent execution by our entire organization and our newest foundry partner, Fujitsu Limited. Lattice announces its products when we can firmly commit samples to our customers within weeks, not months or years. We are convinced that customers are well served only when real products are available in real time," Kopec added. Remaining LatticeECP and LatticeEC devices are expected to sample over the next three months, with production release scheduled in the first quarter of 2005.

New Devices Added To Address Customer Needs

Lattice has also expanded its LatticeECP and LatticeEC FPGA families with the addition of 33K LUT devices. The LatticeECP33 and LatticeEC33 FPGAs provide optimal support for customers whose requirements fall between the previously announced 20K LUT and 40K LUT devices. "The LatticeECP and LatticeEC product families have to a large degree been designed by our customers," Kopec said. "When they told us they needed a device between 20K and 40K LUTs, we responded quickly."

About the LatticeECP and LatticeEC FPGA Families

Announced June 28, 2004, the LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.

Design Tools and IP Support

Design support for the LatticeECP-DSP and LatticeEC devices is provided by Lattice's next-generation software suite of design tools, ispLEVER(R) version 4.1. These ispLEVER design tools provide designers with access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity.

An extensive range of IP (intellectual property) cores, particularly suited for high-volume applications, will be available from both Lattice and its IP partners. Complete details of IP support are being announced separately throughout 2004.

Availability and Pricing

The ECP-DSP20 and EC20 devices are available now in 484-ball fpBGA and 672-ball fpBGA packages in commercial and industrial temperature range options. The LatticeECP and LatticeEC families are available in low-cost packaging options supporting a pin-compatible footprint throughout the family for easy density migration. Current pricing in 1,000 piece quantities for the LatticeECP20 and LatticeEC20 starts at $53 and $44, respectively.

About Lattice Semiconductor

Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP(TM) Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC(TM)), and Programmable Digital Interconnect (GDX(TM)). Lattice also offers industry leading SERDES products. Lattice is "Bringing the Best Together" with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone [phone], fax [phone]. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP, LatticeECP-DSP, LatticeEC, ISP, ispLEVER, GDX, PAC, sysDSP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.