Lattice Semiconductor Announces Next Generation ispLEVER Design Tools.

Business Editors & Technology Writers

HILLSBORO, Ore.--(BUSINESS WIRE)--April 22, 2002

--Comprehensive, Integrated Tools Support In-System Programmable(TM)

Logic Design; Includes New Features and Industry Leading CAE Tools--

Lattice Semiconductor Corporation (Nasdaq:LSCC), the world's largest supplier of in-system programmable (ISP(TM)) PLDs, today announced the release of its next-generation ispLEVER(TM) design tools, "The Simple Machine for Complex Design".

The ispLEVER tools, fully integrated with leading CAE synthesis and simulation tools, are designed to provide powerful new capabilities and easy to use features in a single design flow supporting Lattice ispMACH(R), ispLSI(R), ispGDX(R), ispGAL(R), and GAL(R) devices, including the revolutionary new ispMACH 5000VG and ispMACH 4000 CPLD device families.

The ispLEVER system builds on the powerful Project Navigator used in Lattice's ispDesignEXPERT tools, with enhancements to the GUI to support new features and device families. Lattice has also added a completely new Constraints Editor with multiple entry options and enhanced functionality. The Constraints Editor allows the user to add pin and signal attributes, including selection of Lattice's new sysIO(TM) advanced I/O standards, to any pin quickly and easily. A graphical pin editor is included so users can simply drag-and-drop from an automatically generated signal list to a selected device package pin.

The ispLEVER Performance Analyst(TM) with SpeedSEARCH(TM), familiar to ispMACH and MACH device users, has been enhanced to support static timing analysis for all Lattice device families. Performance Analyst gives the user complete flexibility to select and evaluate any speed grade of a device without design recompilation. It supports fast, detailed analysis of operating frequency (fMAX), logic delay (tPD), clock-to-output delay (tCO), and input set-up time (tSU), as well as other critical timings at the click of a button. With Lattice's revolutionary SpeedSEARCH capability, timing analysis results may be detailed and analyzed with a minimum of effort.

The ispLEVER fitter is tuned to take full advantage of Lattice's many architectural innovations and includes global timing driven design for highest performance in a push button flow. With the ispEXPLORER(TM) tool, users can easily set up multiple compiler runs using a variety of compiler settings through a graphical interface. This unique feature provides users with a powerful tool for finding the optimum design compiler settings quickly by allowing them to view the results of multiple compilation runs in a straightforward spreadsheet-like table. This allows the user to quickly select the settings that give the best results as the design evolves.

The user's standard internet browser has also been added to the Lattice tools arsenal by providing the facility for both HTML-based report viewing and navigation and the latest innovation from Lattice, ispUPDATE(TM). The ispUPDATE feature allows the user to query the Lattice web site for the latest software enhancements and device support at any time and to download new support instantly via the Internet.

Lattice continues to lead all PLD suppliers by integrating and supplying industry leading synthesis and simulation tools from Mentor Graphics(R) and Synplicity(R). The ispLEVER tools support both Leonardo Spectrum(R) and Synplify(R) VHDL and Verilog synthesis tools and the ModelSim(R) RTL and Timing Simulation tool.

To complete the design flow, Lattice's ispVM(TM) System is integrated with the ispLEVER design tool. This highly efficient programming software interface includes device programming support for all Lattice ISP devices and includes JEDEC, SVF, and full support for the IEEE 1532 ISC programming standard.

Lattice's ispLEVER design tools are designed to extract the highest performance and utilization from the industry's most diverse and powerful portfolio of In-System Programmable logic devices. The ispLEVER system has been thoughtfully architected as the platform for future Lattice programmable design flows as well. The ispLEVER design tools will also support Lattice's recently purchased ORCA(TM)-Foundry FPGA and FPSC design tools in a future release.

Availability

The ispLEVER design tools are available for immediate shipment starting at $995 list price. Contact a Lattice Semiconductor Corporation sales representative for further information.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP programmable logic device (PLD), Field Programmable Gate Array (FPGA) and Field Programmable System-on-a-Chip (FPSC) devices. Lattice offers total solutions for today's advanced logic designs. Lattice introduced in-system programmable CPLDs to the logic industry in 1992.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone [phone], FAX [phone]. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties, including technological and product development risks, changes to industry standards, and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor, L (stylized) Lattice, ISP, In System Programmable, ispMACH, ispLSI, ispGAL, GAL, ispGDX, ispLEVER, ispDesignEXPERT, ispEXPLORE, ispUPDATE, ORCA, Performance Analyst and SpeedSEARCH are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Mentor Graphics, Leonardo Spectrum and ModelSim are registered trademarks of Mentor Graphics Corporation in the United States and/or other countries. Synplicity and Synplify area registered trademarks of Synplicity, Inc. in the United States and/or other countries.