Lattice Releases 3rd Generation SuperFAST CPLD Architecture Supporting 1.8 and 2.5 Volts; ispMACH 4000 ISP CPLDs Launch Lattice's BFW III Products.

Business Editors, Technology Writers

HILLSBORO, Ore.--(BUSINESS WIRE)--Dec. 3, 2001

Combines Industry-Leading Performance with Lowest Power Consumption

Lattice Semiconductor Corporation (Nasdaq:LSCC) today announced the immediate availability of the first devices in its ispMACH(tm) 4000 SuperFAST(tm) family, the 256 macrocell ispMACH 4256 and the 512 macrocell ispMACH 4512.

Both devices are offered in 2.5- and 1.8-volt power supply versions, designated the ispMACH 4000B and ispMACH 4000C devices, respectively. The ispMACH 4000C, the industry's first 1.8-volt in-system programmable (ISP) CPLD family, continues Lattice's tradition of being first-to-market with support for new, lower voltage standards. The ispMACH 4000 devices couple industry leading speed performance with the lowest dynamic power consumption available while supporting I/O standards between 3.3 and 1.8 volts. Through the use of cutting edge 0.18-micron Electrically Erasable (E2CMOS(R)) non-volatile process technology, Lattice is able to deliver these new capabilities in a cost-effective manner. The release of the family represents the start of the third generation of Lattice's Big, Fast and Wide (BFW III) products.

"We are excited to launch a CPLD family with such extraordinary capabilities," said Steven Laub, president of Lattice. "The ispMACH 4000 family, the first family of our BFW III generation, continues Lattice's tradition of PLD innovation and further extends our leadership position in CPLD solutions."

The ispMACH 4000 family provides logic designers with a single architecture that covers a wide range of logic capacities, with 6 logic density options from 32 to 512 macrocells in a variety of advanced package and I/O options. I/O counts range from 30 to 208 across the family. The devices provide optimal logic implementation for many glue logic, state machine, decoder, bridging, power-up, and signal handshaking functions. These functions are critical for the implementation of many high performance computing, communications, and industrial applications.

SuperFAST Performance

The ispMACH 4256 devices provide 3.0ns pin-to-pin delay (tPD), 3.0ns clock-to-output delay (tCO), 2.0ns set-up time (tS), and 300MHz operating frequencies (fMAX), 40% faster than available competitive devices. The ispMACH 4512 devices provide 3.5ns tPD, 3.5ns tCO, 2.4ns tS and 256MHz fMAX, 36% faster than competitive devices. Future members of the family are expected to reduce pin-to-pin delays to 2.5ns and provide operating frequencies well above 300MHz.

Lowest Dynamic Power Consumption

Traditionally achieving low power consumption had primarily been of interest to designers of equipment with limited available power. However, designers of high performance computing and communications systems, which traditionally have had comparatively large power budgets, are increasingly interested in lowering power consumption to reduce operating cost and enhance system reliability. Lattice designed the ispMACH 4000 family to provide significantly lower power for these applications. Novel design techniques, coupled with the use of low power non-volatile cells, allows static current to be reduced to as low as 1 milliamp. The use of a 1.8-volt core provides reduced dynamic power consumption for the family. As a result, the ispMACH 4256 device typically dissipates 78% less power at 100MHz than other commercially available 2.5-volt CPLD solutions.

Supports LVTTL and Multiple LVCMOS Standards

The ispMACH 4000 devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5, and 1.8-volt outputs. Device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. This approach, coupled with the availability of both 2.5- and 1.8-volt devices, gives designers the flexibility needed in today's multi-voltage environments.

All ispMACH 4000 devices are also Boundary Scan Testable and in-system programmable through an IEEE 1149.1-compliant JTAG boundary scan interface. The programming of the devices is fully compliant with the IEEE 1532 standard as well.

Design Tools

The ispMACH 4000 family is supported by Lattice's new ispLEVER(tm) design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance of the ispMACH 4000 devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions.

Price and Availability

The ispMACH 4256B and ispMACH 4256C are available now in 100- and 176-pin Thin Quad Flat Pack (TQFP) and 256-ball fine pitch Ball Grid Array (fpBGA) packaging. The ispMACH 4512B and ispMACH 4512C are similarly offered in footprint-compatible 176-pin TQFP and 256-ball fpBGA package options. The other devices in the family are expected to be released in the first half of 2002. For high-volume applications, pricing for the ispMACH 4256 is projected to be as low as $6.50 during the second half of 2002, while the ispMACH 4512 will be priced from $15.00.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP(TM) programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone [phone], FAX [phone]. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), in-system programmable, ispLEVER, SuperFAST, ispMACH, E2CMOS, ISP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.