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Lattice Releases 3.3-Volt Family of High I/O ispGDX Devices.


HILLSBORO, Ore.--(BUSINESS WIRE)--July 26, 1999--

-    The ispGDXV(tm) family of 3.3-volt in-system programmable digital
     crosspoint devices support I/O densities from 80 to 240 pins
-    High I/O, in-system programmable devices provide unique solution
     for high integration, board-level signal routing and interfacing


Lattice Semiconductor Corporation (NASDAQ NASDAQ
 in full National Association of Securities Dealers Automated Quotations

U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on
: LSCC LSCC Lake-Sumter Community College (Florida)
LSCC Lattice Semiconductor Corporation (stock symbol)
LSCC Lawson State Community College (Alabama) 
) today released the first of a family of high performance, 3.3- volt in-system programmable digital crosspoint devices. Based on a second generation ispGDX architecture, this family delivers highly integrated signal routing and interface solutions for today's high performance electronic systems.

The ispGDX160V is the first member of the new ispGDXV family. The ispGDXV architecture is a functional superset A group of commands or functions that exceed the capabilities of the original specification. Software or hardware components designed for the original specification will also operate with the superset product. However, components designed for the superset will not work with the original.  of the earlier 5-Volt ispGDX family with new features, higher I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 options and a 3.3-Volt logic core. The ispGDXV family offers a new programmable MUX width for MUX chaining and supports up to 16:1 real-time multiplexing, a unique capability among programmable devices. The family supports I/O densities from 80 up to 240 and includes other features such as a bus hold latch per I/O, programmable clock enable logic, hot socketing tolerance, output slew rate control and full boundary scan test and in-system programming support (IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields.  1149.1 compliant).

The logic architecture of the ispGDX160V features 160 programmable I/O cells interconnected by a Global Routing Pool (GRP GRP Group
GRP Group (file name extension)
GRP Glass Reinforced Plastic
GRP Gastrin-Releasing Peptide (biology)
GRP Gross Rating Point (advertising) 
) that delivers fast operation: input-to-output signal delays (Tpd) of 5ns, clock-to-output delays (Tgco) of 5ns and pin-to-pin operating frequencies (Fmax) of 111MHz. It is offered in advanced 208- and 272-ball BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used.  packages as well as a 208-pin PQFP (Plastic Quad Flat Package) Refers to many varieties of QFP chip packages, which are molded in plastic. See QFP.  (plastic quad flat pack) package. The ispGDX160V is available in both commercial and industrial operating ranges.

Like all ispGDX devices, this new device is optimized for digital signal interface Digital Signal Interface (DSI) is a protocol for dimming stage lighting (initially electrical ballasts). It was created in 1991 by Austrian company Tridonic ATCO and is based on Manchester-coded 8-bit protocol, data rate of 1200 baud, 1 start bit, 8 data bits (dimming  and routing applications, and represents a new class of high-density programmable components distinct from complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) that supports board-level rather than chip-level logic interface solutions. The devices are ideal for board-level signal switching and multiplexing applications including wide bus steering, multi-port memory interfaces, and standard interface logic integration.

"The ispGDX160V continues our commitment to systems designers migrating to low-voltage designs," said Steve Stark, Lattice's director of component marketing. "The ispGDXV family supports a wider range of signal routing and interface applications with expanded functionality and I/O count."

ispGDX and ispGDXV devices are supported by Lattice's ispGDX Development System software. Device design in this environment is done using a simple, yet powerful, Lattice Hardware Description Language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog.  specifically designed for the ispGDX architecture. It also interfaces to existing 3rd party simulation tools for complete timing simulation in industry standard formats.

Price and Availability

The 5ns speed grade ispGDX160V in the 208 ball BGA package is available now and priced at $9.95 in high volume quantities. Reader Contact: Steve Stark, Director of Component Marketing (503) 268-8000

About Lattice Semiconductor and Vantis

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP programmable logic devices (PLDs) and offers total solutions for today's advanced logic designs. Lattice introduced in-system programmability to the logic industry in 1992. In June 1999, Lattice acquired Vantis, the corporation that invented the PAL(R) device and PLD switch matrix architecture, from AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. . With nearly double the R&D and sales resources, the resulting integrated company will focus on delivering logic products that satisfy the performance, density and ease-of-use requirements of its customers.

Lattice/Vantis products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000; FAX 503-268-8037. For more information on Lattice Semiconductor or Vantis Corporation, access our World Wide Web sites at http://www.latticesemi.com.

E2CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. , GAL, ispGAL, ispLSI, UltraMOS, Lattice Semiconductor, L (stylized styl·ize  
tr.v. styl·ized, styl·iz·ing, styl·iz·es
1. To restrict or make conform to a particular style.

2. To represent conventionally; conventionalize.
) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. ISP, ispDOWNLOAD, ispDS+, ispGDS, ispGDX, ispGDXV are trademarks of Lattice Semiconductor Corporation. All other brand names or product names are trademarks or registered trademarks of their respective holders.
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No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1999, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Date:Jul 26, 1999
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