Lattice Announces ispLEVER 5.0 Programmable Logic Design Tool Suite.HILLSBORO, Ore. -- - Unprecedented ease-of-use, new features and exceptional performance; full design support for all Lattice digital programmable logic devices includes the new LatticeXP FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. family - Lattice Semiconductor Lattice Semiconductor Corporation (NASDAQ: LSCC) is a United States based manufacturer of high-performance programmable logic devices (FPGAs, CPLDs, & SPLDs). The Oregon based company is the number four ranked company in world market share for FPGA devices,[1] Corporation (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : LSCC LSCC Lake-Sumter Community College (Florida) LSCC Lattice Semiconductor Corporation (stock symbol) LSCC Lawson State Community College (Alabama) ) today announced the immediate availability of its ispLEVER(R) 5.0 programmable logic See PLD. design tool suite. Major additions and improvements to design flow and documentation make the ispLEVER features and point tools easy to learn and easy to use. Exceptional performance continues to be a hallmark of ispLEVER software, with design frequency, logic utilization and compilation time all substantially improved. Lattice ispLEVER 5.0 includes support for the new LatticeXP(TM) non-volatile, infinitely reconfigurable FPGAs. Lattice ispLEVER 5.0 provides instant access not only to the latest ispXP(TM) technology, but also to all Lattice FPGA, FPSC FPSC Florida Public Service Commission FPSC Financial Planners Standards Council (Canada) FPSC Field Programmable System Chip (Lucent Technologies) FPSC Fundación Promoción Social de la Cultura , CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. and SPLD (Simple PLD) A programmable logic device that provides a small logic block that can be programmed. The logic block typically contains a handful of macrocells, which have multiple inputs and the ability to perform a limited amount of logic. programmable devices. The ispLEVER tool suite is available in Windows, UNIX UNIX Operating system for digital computers, developed by Ken Thompson of Bell Laboratories in 1969. It was initially designed for a single user (the name was a pun on the earlier operating system Multics). and LINUX versions. "Our customers can unleash the power of Lattice programmable logic devices effectively and efficiently with a design system that is extraordinarily user friendly, offers exceptional functionality and performance and is now value priced at $695," said Stan Kopec, Lattice vice president of corporate marketing. Lattice vice president of software Chris Fanning said, "We've made ispLEVER 5.0 easier to learn and use than ever before, while adding many new and enhanced features and point tools. At the same time, our logic optimization Logic optimization a part of logic synthesis, is the process of finding an equivalent representation of the specificied logic circuit under one or more specified constraint. Generally the circuit is constrained to minimum chip area meeting a prespecified delay. engine has been enhanced to give unprecedented performance and quality of results." Best of breed synthesis and simulation The ispLEVER 5.0 tool suite includes Synplicity's Synplify(R) software for Lattice 8.0 synthesis. This latest version of Synplify improves both speed and quality of results. "Close collaboration over years of partnership with Lattice has now raised the bar for FPGA performance," said Andy Haines, vice president of marketing for Synplicity. "The formidable combination of Synplify and ispLEVER software with the new Lattice FPGA silicon sets a new performance benchmark for the industry. We're excited about our recently expanded OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and agreement with Lattice, and look forward to delivering exceptional performance to our mutual customers for many years to come." The ispLEVER 5.0 release marks the full integration and shipment of the Mentor Graphics(R) Precision RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; (R) synthesis and ModelSim(R) simulation tools with the Lattice design tool suite. "This development is especially important for FPGA designers because it is the first time that commercial, advanced versions of synthesis and simulation tools for complex FPGA design have been offered via any OEM offering to date," said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics. "Through our agreement with Lattice, we have opened up the full breadth of Mentor's superior FPGA design flows and capabilities to our mutual customers, resulting in improved overall productivity and significantly lower silicon costs." Ease of use, ease of learning emphasized Significant additions and enhancements to documentation and tutorials make learning and mastering the ispLEVER design environment easier than ever. Special emphasis has been placed on providing tutorials and examples throughout ispLEVER's design flow and point tools. Learning resources have been comprehensively updated and integrated, including a new, faster help system with links to datasheets and resources on Lattice's website, www.latticesemi.com Robust functionality Top-level schematic design has been added to ispLEVER 5.0, which allows the user to create design function blocks and quickly visualize the entire design in a graphical representation. This not only helps partition the design into manageable elements, but also simplifies the design review process. Every point tool in ispLEVER 5.0 also has been enhanced. The Module/IP Manager GUIs have been streamlined for better ease of use, and many new IP modules have been added for customers' designs. Over 20 new DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive elements have been added to the ispLEVER DSP design library; the I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output Assistant, which facilitates complex I/O assignment and rule checking, has been upgraded; significant enhancements have been made to the Floorplanner to provide additional functionality, including multiple windows; the accuracy and flexibility of the Power Calculator have been enhanced; and the ispTRACY(TM) Logic Analyzer provides new cross-referencing, core integration facilities and optimized displays. A complete list of new ispLEVER 5.0 features and enhancements can be viewed at http://www.latticesemi.com/ New product packaging and starter system upgrade The ispLEVER 5.0 release marks a major advancement in the way ispLEVER tools are configured and licensed. All customers now have access to design tools for all Lattice products, providing unmatched value to the user. The downloadable ispLEVER-Starter configuration has also been expanded to include support for the entire LatticeEC(TM) FPGA family as well as added support for LatticeECP-DSP(TM) devices. Availability and pricing The ispLEVER 5.0 HDL-BASE design tools for Windows, now supporting all Lattice programmable logic families and including ModelSim LE, Precision RTL Lattice Edition and Synplify 8.0, is list priced at $695 and is available immediately. UNIX and LINUX versions are also available. About Lattice Semiconductor Lattice Semiconductor Corporation provides the industry's broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. ), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC(R)) and Programmable Digital Interconnect Devices (ispGDX(R)). Lattice also offers industry leading SERDES See serializer/deserializer. products. Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com Statements in this news release looking forward in time are made pursuant to the safe harbor Safe Harbor 1. A legal provision to reduce or eliminate liability as long as good faith is demonstrated. 2. A form of shark repellent implemented by a target company acquiring a business that is so poorly regulated that the target itself is less attractive. provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party software suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements. Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispLEVER, ispLeverDSP, LatticeECP-DSP, LatticeEC, LatticeXP, ispTRACY, ispXP, ispGDX, ispPAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders. |
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