Lattice Announces ispLEVER 4.1 Design Environment for New LatticeECP-DSP and LatticeEC FPGAs.HILLSBORO, Ore. -- Lattice Semiconductor (Nasdaq:LSCC LSCC Lake-Sumter Community College (Florida)
LSCC Lattice Semiconductor Corporation (stock symbol)
LSCC Lawson State Community College (Alabama) ):
--Enhanced design tools now available in Linux-based configuration; include new synthesis and simulation tools from Synplicity and Mentor Graphics; provide support for all Lattice programmable logic products
Lattice Semiconductor Corporation (Nasdaq:LSCC) today announced its ispLEVER(R) version 4.1 design tool suite, which includes design support for the recently introduced LatticeECP-DSP(TM) and LatticeEC(TM) FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. device families.
The Lattice ispLEVER software suite is a well established and broadly installed programmable logic design tool platform, supporting all Lattice programmable logic devices. The ispLEVER solution includes all the tools needed to move a programmable logic design from concept through implementation. This complete software suite includes tools for efficient design entry, project management, design fitting, place and route, floorplanning, device programming, on-chip logic analysis and more. The ispLEVER design tools also include third party solutions for HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. synthesis and simulation from Synplicity and Mentor Graphics, assuring users of superior synthesis and simulation results.
New ispLEVER 4.1 enhancements provide users a simple and straightforward upgrade path to designing with the new Lattice FPGA families, while retaining the familiar and easy-to-use ispLEVER interface. This new software release also improves the design libraries and fitting engines for all Lattice programmable logic families, and adds support for the new ispXPGA-E(TM) low-cost FPGAs and ispGDX2-E(TM) programmable crosspoint switches. The ispLEVER 4.1 release also includes new versions of third party synthesis and simulation tools from Synplicity and Mentor Graphics and, for the first time, supports the Linux OS.
"Our new ispLEVER 4.1 design tools will unlock the unique capabilities of our LatticeECP-DSP and LatticeEC FPGA technologies," said Stan Kopec, Lattice vice president of corporate marketing. "With ispLEVER 4.1, designers can quickly implement their FPGA designs on these exciting new product families that have been optimized for both economy and exceptional performance, while taking advantage of industry-leading features that include dedicated high performance DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive blocks, DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM.
DDR - Double Data Rate Random Access Memory interfaces and low-cost memory configuration options."
Lattice vice president of software Chris Fanning said, "ispLEVER 4.1 delivers enhanced capability, performance, and ease-of-use to our customers. Our continued consultations with experienced FPGA designers provide invaluable input to our development process and help us deliver a first-class FPGA design environment."
In anticipation of the growing demand for Linux-based design solutions, ispLEVER 4.1 will be available on the Red Hat Enterprise Linux Red Hat Enterprise Linux (often abbreviated to RHEL) is a Linux distribution produced by Red Hat and targeted toward the commercial market, including mainframes. Red Hat commits to supporting each version of RHEL for 7 years after its release. version 3 operating system. The ispLEVER 4.1 design tools also include DSP blocks for use in the MATLAB/Simulink DSP design environment, available separately from The Mathworks. These DSP blocks can be used to build DSP solutions, within the MATLAB/Simulink environment, that can then be exported in HDL optimized for the LatticeECP-DSP FPGA architecture.
Availability and pricing
The ispLEVER 4.1 design tools are available now in a variety of PC-, UNIX- and Linux-based configurations. List prices begin at $995. All registered users of Lattice software with a valid maintenance agreement will receive the 4.1 upgrade at no charge within the next thirty days.
About the LatticeECP-DSP and LatticeEC FPGA Families
Introduced June 28, 2004, the LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP ("EConomyPlusDSP") products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC ("EConomy") FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. marketplace.
About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC FPSC Florida Public Service Commission
FPSC Financial Planners Standards Council (Canada)
FPSC Field Programmable System Chip (Lucent Technologies)
FPSC Fundación Promoción Social de la Cultura ) and high-performance ISP (1) See in-system programmable.
(2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. (TM) Programmable Logic Devices (PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. ), including Complex Programmable Logic Devices (CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. ), Programmable Analog Chips (PAC(TM)), and Programmable Digital Interconnect (GDX GDX Magadan, Russia - Magadan (Airport Code)
GDX Gamma Delta Chi (fraternity)
GDX Generic Digital Crosspoint (TM)). Lattice also offers industry leading SERDES See serializer/deserializer. products. Lattice is "Bringing the Best Together" with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor Safe Harbor
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2. A form of shark repellent implemented by a target company acquiring a business that is so poorly regulated that the target itself is less attractive. provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeEC, LatticeECP, LatticeEC-DSP, GDX, ISP, ispGDX, ispLEVER, ispXPGA, PAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
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