LSI LOGIC COMPLETES CHARACTERIZATION OF MEMORY INTERFACE CORES.

LSI Logic Corporation (NYSE:LSI) has completed silicon characterization of Gflx (0.11-micron) DDR-SDRAM memory interface cores in low cost packages and RLDRAM-II and FCRAM-II memory interface cores at the highest speeds, 400MHz/800Mb/s. These high-speed memory interface cores provide designers with a physical layer interface that can be quickly and easily integrated into ASIC designs.

"This development underscores LSI Logic's commitment to providing risk-free high-speed memory interface solutions," said William Lau, director of Memory Interface and Signal Integrity, LSI Logic. "We have demonstrated that our memory interface solutions offer superior performance and our signal integrity expertise translates into lower system costs and faster time-to-market for our customers."

The Gflx DDR1-SDRAM cores are characterized in silicon up to 266 MHz/533Mega-bits-per-second (Mbps) in wirebond packages under best, worst and nominal process, voltage and temperature (PVT) conditions. This enables devices with low-cost wirebond packages while maintaining adequate headroom over the memory industry's highest DDR-SDRAM speeds. System designers can take advantage of this headroom by easing board design constraints, resulting in lower overall system costs.

Gflx RLDRAM-II and FCRAM-II cores are characterized in silicon up to 400MHz/800Mbps. The superior signal integrity of the HSTL I/Os combined with the timing-closed hard macros allow customers to rapidly design their ASICs and unlock the performance benefits of low-latency, high bandwidth RLDRAM and FCRAM memories at a reduced risk.

LSI Logic provides a wide range of memory interface cores and I/O buffers for DDR-SDRAMs, DDR2-SDRAMs, QDR-SRAMs RLDRAMs and FCRAMs. The cores and I/O buffers provide a timing-closed solution allowing customers to reduce chip development time and speed time-to-market.

About CoreWare

The LSI Logic CoreWare IP library provides the industry's most comprehensive set of IP solutions that are proven and designed to work seamlessly with the standard-cell ASIC and RapidChip Platform ASIC design flows. CoreWare IP includes GigaBlaze and HyperPHY high-speed standards-compliant SerDes, high-performance ARM and MIPS processors and associated systems, licensable ZSP DSP cores, processor peripherals and AMBA on-chip-bus structures, USB cores, Memory PHYs and Controllers, Ethernet MAC and PHY cores, PCI Express, XGXS, SPI4.2 and other protocol layer IP. Customers can leverage CoreWare IP solutions to significantly reduce risk and turn-around times with complex SoC designs. Additionally, a worldwide IP support organization is available to assist customers in all aspects of CoreWare SoC design.

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