LG Adopts Apache's PsiWinder for Full-Chip Clock Jitter and Critical Path Timing Sign-off.

PsiWinder Delivers Silicon Correlated Results for SoC Jitter Analysis

MOUNTAIN VIEW, Calif. -- Apache Design Solutions, the technology leader in power sign-off and complete silicon integrity platform solutions for system-on-chip (SoC) designs, today announced that LG used PsiWinder to accurately measure full-chip jitter on their clock network and to optimize their design to minimize the impact of noise. By using PsiWinder for full-chip jitter analysis, LG is able to reduce the risk of silicon re-spin due to jitter induced timing failures.

The impact of jitter noise on the clock tree network has become a critical design concern as process nodes move beyond 90nm, especially for high-performance multi-clock designs. But traditional methods have not supported a quantitative way to determine jitter noise on a clock network, as jitter analysis is a complex issue attributed by the combination of power noise, package noise, crosstalk noise, etc. and is dependent on the functional operation mode. PsiWinder, a full-chip noise analysis tool with Spice-level accuracy, considers the concurrent effect of dynamic power and ground noise, LC resonance and crosstalk, resulting in accurate measurements of jitter noise on the clock tree. PsiWinder has been in production use by several customers for over a year and has produced silicon correlated results as close as 5% of measurement.

"By using PsiWinder from Apache, we were able to quantitatively determine the full-chip clock jitter caused by switching noise, including inductive and crosstalk effects," said Woo-Hyun Paik, vice president of LG Electronics. "We were very pleased with how well PsiWinder's results correlated with our silicon measurements."

"Jitter noise has become one of the key design challenges at 90nm and below processes, and our customers are looking for solutions that can accurately determine the impact of jitter on their clock tree," said Dian Yang, General Manager and Vice President of Product Management at Apache. "We are pleased to see an increasing adoption of PsiWinder by leading semiconductor companies to address this critical need."

About PsiWinder

Clock network integrity (jitter) and critical path timing sign-off solution that considers the concurrent and interdependent effects of signal integrity (crosstalk noise) and power integrity (dynamic voltage drop and ground bounce, as well as package induced noise) on clock jitter and critical path timing. Certified by TSMC's Reference Flow 7.0, PsiWinder delivers Spice-level accuracy with full-chip capacity, enabling designers to gain much more realistic view of clock jittering and skew, as well as the setup and hold time violations in the critical paths.

About Apache Design Solutions

Apache delivers the leading power sign-off solution adopted by 70% of top semiconductor companies and a complete platform solution for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache's innovative platform considers all sources of noise that impacts the design -- such as power, signal, package/system IO, substrate and temperature -- Apache's silicon integrity platform enables designers of leading networking, wireless, communication, consumer and semiconductor companies to detect, fix and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are certified by TSMC's 5.0, 6.0 and 7.0 Reference Flow (NYSE:TSM). Apache has direct sales and support offices worldwide with over 40 customers, including eight of the top 10 semiconductor companies. For more information, visit www.apache-da.com.

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, Sahara-PTE, Vectorless Dynamic and ASIP are trademarks of Apache Design Solutions, Inc.