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JasperGold Adds Proof Accelerators for Fast, Thorough Verification.

Speeds End-to-End Proofs for Data Packet Integrity, RAM, and Multipliers

MOUNTAIN VIEW, Calif. -- Jasper Design Automation, provider of advanced formal technology solutions, today announced the addition of three new Proof Accelerators to its JasperGold[R] Verification System. Proof Accelerators increase the power, the capacity and the performance of formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 by significantly reducing the state-space of a design through optimized modeling of common design functions.
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Proof Accelerators & JasperGold

JasperGold provides rapid bug detection and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits.  as well as end-to-end full proofs of expected design behavior, and provides valuable insight across the design cycle in architectural analysis, RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences;  debug, verification and post silicon debug. Jasper's Proof Accelerators speed up formal proofs to significantly reduce verification complexity, and combined with Design Tunneling[TM] can consistently perform full proofs on properties where other formal tools fail to converge, with an average 10x proof capacity advantage over competitors.

Availability

A selection of Proof Accelerators for JasperGold are currently available to handle myriad applications, including data transfer integrity, FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods.

FIFO - first-in first-out
 and memory modeling, data synchronization across clock domains, cache verification, and more. For complete details contact Jasper at: info@jasper-da.com.

About Jasper Design Automation

Jasper delivers industry-leading EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California For the census-designated place, see Mountain View, Contra Costa County, California. For other places called "Mountain View", see .
Mountain View is a city in Santa Clara County, in the U.S. state of California. The city gets its name from the views of the Santa Cruz Mountains.
, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI (Return On Investment) The monetary benefits derived from having spent money on developing or revising a system. In the IT world, there are more ways to compute ROI than Carter has liver pills (and for those of you who never heard of that expression, it means a lot). : reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.

Jasper Design Automation, the Jasper Design Automation logo, ActiveDesign, Behavioral Indexing, and JasperGold are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.
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Publication:Business Wire
Date:Apr 20, 2009
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