Jasper Design Automation Names Dale Hayes Vice President of Sales; 20-Year EDA and Electronics Veteran Brings Expanded Sales Expertise To Seasoned Management Team.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--June 3, 2004 Jasper Design Automation, provider of breakthrough high-level formal verification
In the context of hardware and software systems, formal verification solutions for provably correct design, today announced the appointment of Dale Hayes Dale Hayes (born 1 July 1952) is a South African golfer. Career outline Hayes won the 15-17 Boys category at the Junior World Golf Championships in 1969. He turned professional the following year and quickly became a successful pro. as its new Vice President of Sales. Mr. Hayes' sales and management expertise provides an excellent complement to Jasper's impressive management team. "Having very successfully sold and managed emerging and established EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. technologies and tools into industry-leading chip and systems companies, Dale brings to Jasper the key ingredients to successfully deliver our ground-breaking formal verification products to the worldwide market," said Kathryn Kranen, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and president for Jasper Design Automation. "His experience and industry insights promise to drive Jasper to a position of industry leadership in the functional verification marketplace." "I've joined Jasper at a very important time, when the industry is searching for solutions to the increasingly complex challenges of design verification," said Dale Hayes. "When I was introduced to Jasper's innovative and ground-breaking technology, and its extraordinarily talented and committed team, I could see that something big was happening at Jasper. Now that I've had a chance to see the enthusiasm of Jasper's customers, and the high value they are receiving, I am convinced that we are hitting the verification sweet spot." Prior to joining Jasper, Mr. Hayes served at Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. as North America New Technologies Sales Director for acquired new businesses. Most recently Mr. Hayes managed the successful sales and operational integration of the Verplex acquisition, the Verplex North America Sales and AE Teams, the Get2Chip Sales Team, and sales of the Encounter Test Products acquired from IBM (International Business Machines Corporation, Armonk, NY, www.ibm.com) The world's largest computer company. IBM's product lines include the S/390 mainframes (zSeries), AS/400 midrange business systems (iSeries), RS/6000 workstations and servers (pSeries), Intel-based servers (xSeries) . Before Cadence, Mr. Hayes was Sales Director for the Eastern US and Canada, for Simplex Solutions as the company grew from $5 Million to $50 Million in revenue from 1998 to 2002 (IPO (Initial Public Offering) The first time a company offers shares of stock to the public. While not a computer term per se, many founders, employees and insiders of computer companies have found this acronym more exciting than any tech term they ever heard. in 2001), and then was acquired by Cadence in 2002. Previous to this, Mr. Hayes held positions in sales and engineering at Cadence, BNR BNR Bulgarian National Radio BNR Banca Nationala a României (National Bank of Romania) BNR Biological Nutrient Removal (sewage treatment) BNR Bell Northern Research BNR Body Not Recovered BNR Big Nerd Ranch (Nortel Networks), Alcatel Network Systems and General Electric Semiconductor. Mr. Hayes holds a B.S. degree in Computer Science, from North Carolina State University History
About Jasper Design Automation Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company headquartered in Mountain View, CA. Enabling the first Provably Correct Design methodology, Jasper's static block-level verification solution for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designs uses breakthrough formal verification technology to exhaustively verify functional behaviors of RTL blocks without simulation or test vectors. JasperGold analyzes a block against high-level requirements derived from the micro-architecture spec, and either isolates bugs that cause the requirements to fail, or proves the requirements true for all legal input sequences. Pre-verified, bug-free blocks are then integrated into system-level verification trimming months off the verification schedule. For further details on how to drive higher design quality and shorter schedules, please visit: http://www.jasper-da.com. Jasper Design Automation, the Jasper Design Automation logo, Tempus Quest, JasperGold and Jasper Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies. |
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