Jasper Design Automation Integrates Verific's SystemVerilog Component Software With JasperGold Verification System; Formal Verification Supplier Commends Verific's Responsiveness, Commitment to Jasper's Success.ALAMEDA, Calif. -- Verific Design Automation today announced that Jasper Design Automation, provider of breakthrough high-level formal verification
In the context of hardware and software systems, formal verification solutions, has successfully integrated Verific's SystemVerilog Component Software with JasperGold(R) Verification System. JasperGold System 4.2, featuring SystemVerilog language support, will be demonstrated at the 43rd annual Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) in San Francisco beginning July 24, 2006. "Verific is a superior business partner and we commend them for being responsive and committed to the current market success of JasperGold Verification System," notes Claudionor Coelho, vice president of engineering at Jasper Design Automation. "Without Verific, an internal SystemVerilog development effort would have been a long, difficult process. Verific's language solutions, combined with Jasper's leading assertion synthesis technology, have contributed to our leading position in formal verification for standard assertion and design languages." "Jasper is a highly valued partner, and following on to our close collaboration on PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. , we are excited to work with them on the SystemVerilog solution" says Verific's president, Rob Dekker. "We have built a long-standing relationship with Jasper, delivering a variety of HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. component software packages for JasperGold Verification System." In addition to SystemVerilog component software, Verific offers a number of other hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL) component software packages, all written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms. Products include SystemVerilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and Verilog parsers, analyzers, and elaborators, as well as a register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) database. All products are licensed as source code and come with online support and maintenance. Verific's entire line of HDL Component Software also will be demonstrated during DAC in Booth #3345. To schedule a demonstration, visit Verific's website located at: http://www.verific.com. Or, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. JasperGold is a registered trademark of Jasper Design Automation. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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