JVC Selects Tharas Systems' Hammer Hardware Accelerator to Reinforce Its Verification Flow.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--May 29, 2003

Tharas Systems, Inc., a provider of high-performance, hardware-assisted design verification solutions, announced today that Victor Company of Japan, Limited (JVC) based in Yokohama, Japan has incorporated Hammer hardware accelerator into its verification flow.

"Victor Company of Japan develops leading-edge consumer multi-media products. Verifying functional accuracy of complex multi-media chips and systems using traditional software simulators is a strenuous task. We looked into hardware-assisted simulation accelerators to speed up this process. Hammer offers a compelling alternative. Incorporating Hammer into our verification flow was easy and quick," says Hiroshi Nishiyama, Senior Engineer of Home AV Network Business Unit of Victor Company of Japan, Limited.

"It is our privilege to have JVC as a Tharas customer. JVC and Nishiyama-san has a long history of bringing groundbreaking multimedia products such as VHS-C camcorders and digital cameras to the marketplace. This is a testament to Hammer's innovative 128-way parallel processor technology, Hammer offers a superior solution in terms of capacity, compile times, run times, debug features, ease of use, and scalability over competing products. All this is available at less than one-half to one-third the price of competing systems," notes Rahm Shastry, President and CEO of Tharas Systems.

Tharas Systems' Hammer provides Verilog, VHDL and mixed simulation Accelerators with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Hammer compiles a design at a rate of 10 to 50 Million RTL gate-equivalent designs in as little as one hour on a single workstation vs. 8 hours per Million RTL gate-equivalent for FPGA-based systems. Run times range from 10 to 1000 times faster than the fastest software simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug -- contrast this to dramatic loss of performance during run time of competing FPGA-based systems during debug.

Hammer works with existing RTL and gate-level verification environment. As a result, designers can continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ: SNPS) and Cadence Design Systems, Inc. (NYSE: CDN). Hammer supports design sizes of up to 128 Million Gate-equivalent RTL code, and 16 Gigabyte in hardware. Hammer pricing ranges from US$115,000 to US$1,980,000.

About Tharas Systems

Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer(R) offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/. For more specific product information, email [e-mail] or call 1-408-855-3200

Hammer(R) is a registered trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.