International SEMATECH Transfers First Integrated Low-k Material: JSR LKD-5109 Baseline Moves to Pilot Manufacturing to Accelerate Low-k Development.

Business Editors & High-Tech Writers

SAN FRANCISCO--(BUSINESS WIRE)--July 24, 2002

International SEMATECH's (ISMT) Interconnect Division announced today that it has transferred its low-k baseline process for 200mm to pilot manufacture in ISMT's cleanroom (Advanced Technology Development Facility or ATDF) one full month ahead of schedule. The low-k baseline dual Damascene process flow, using JSR LKD-5109 porous spin-on dielectric material, will accelerate the efforts of ISMT and its partners to develop low-k solutions for the semiconductor industry.

"The insertion of low-k materials into manufacturing is taking longer than expected due to a number of issues, including low strength, poor adhesion, and DUV photo resist poisoning," stated Rod Augur, ISMT's program manager for Cu/low-k interconnect integration. "Nevertheless, the International Technology Roadmap for Semiconductors still calls for low-k values that are only available with porous materials, which places further constraints on unit processes." What is needed, Augur insists, is a steady supply of samples for development by process, chemical, and tool suppliers, to help solve the integration issues of porous ultra low-k materials. ISMT's new low-k baseline will provide these samples.

JSR LKD-5109 is a MSQ (methylsilsesquioxane) based dielectric with k2.2 and pore diameter 2nm. ISMT's baseline process flow uses a dual top hard mask approach (to make litho re-work easier), standard Cu electroplating, and conventional CMP (chemical mechanical planarization). The flow was transferred to ISMT's ATDF on May 31, 2002, and current yields regularly exceed 85% on 0.25micron 360k via chains. Continual process improvement is planned to increase both yield and performance. By year-end, International SEMATECH will qualify the low-k flow on 300mm wafers; ISMT is planning a move to 130nm actual feature sizes in early 2003 as well.

"The challenge of providing ultra low-k materials does not stop with the development of viable, mature precursors," said Navjot Chhabra, director of Interconnect at International SEMATECH. "It's not enough to engineer the low-k alone. These films must be capable of being fully integrated with the appropriate supporting layers and processes, without diminishing electrical and reliability specifications. Our low-k baseline process will help us understand the interactions of the low-k material with novel barriers, new low-k etch stop layers, and non-compromising etches and cleans."

"This is an important milestone in our work on low-k dielectrics," said Chhabra. "It will accelerate our own efforts here at ISMT, and also encourage parallel development by our various partners, to help the industry realize the Roadmap in this critical technology area."

In related news, test wafers developed with JSR LKD-5109 are now available through International SEMATECH (ISMT) for etch, cleans, deposition and CMP studies. The wafers will be offered to semiconductor companies on a limited basis under a supplier agreement between ISMT and JSR.

"We're making these wafers available to give semiconductor companies an opportunity to develop their low-k related products and processes," said Brent Ames, manager of Wafer Services for International SEMATECH. "Low-k dielectrics is a critical challenge for our members as well as the industry at large. By distributing these test wafers, International SEMATECH helps drive the industry to major low-k advancements."

A lower `k-value' dielectric improves chip speed and performance by allowing manufacturers to achieve smaller and higher density semiconductor devices with multi-layer interconnect structures. Spin-on dielectric materials are considered to be an enabling technology that will take the semiconductor industry to the next level in chip performance.

"Our work with ISMT demonstrates the value companies can expect from spin-on low-k dielectrics," said Eric Johnson, Senior VP of JSR Microelectronics. "Our hope is that this, and subsequent product releases, will give the semiconductor community the ability to develop the processes and products necessary to revolutionize the industry."

The test wafers are processed using JSR LKD-5109, which will also be available through ISMT as blanket film wafers.

About International Sematech (www.sematech.org)

International SEMATECH (ISMT) is a global semiconductor technology development consortium that has effectively represented the semiconductor manufacturing industry on innovation issues since 1988. Its members are Agere Systems, AMD, Hewlett- Packard, Hynix, IBM, Infineon, Intel, Motorola, Philips, STMicroelectronics, Texas Instruments and TSMC. ISMT conducts state-of-the-art research and development, and is a highly regarded technology partner whose mission is to promote the interests common to all chipmakers. It has extensive experience collaborating with equipment and materials suppliers, as well as government and academic research centers, to refine the tools and technology necessary to produce future generations of chips.

About JSR Microelectronics (www.jsrusa.com)

Sunnyvale, California-based JSR Microelectronics is an innovation partner for leading semiconductor companies. JSR Microelectronics delivers the quality products and domain expertise necessary to support the current needs and future goals of the semiconductor industry. The company advances industry efforts by developing superior semiconductor materials, including advanced photoresists and is leading the development of Low-k dielectric and CMP consumables. JSR Microelectronics began U.S. operations in 1990 and is part of Tokyo-based JSR Corporation. JSR Corporation has around 3,000 employees worldwide.

NOTE TO EDITORS: In the first sentence of the third paragraph, in the phrase "with k 2.2 and pore diameter 2nm," there should be a tilde between the "k" and "2.2" and a tilde in front of "2nm." The symbols were deleted for transmission purposes only.