Intellitech Launches First Interactive Schematic Based Tool for Probe-Less Electronic System Debug; New Trouble-Shooting Tool Replaces Paper Schematics and Physical Probes.

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SAN JOSE, Calif.--(BUSINESS WIRE)--April 21, 2000

Intellitech, the technology leader in scan-based debug and test, announced the availability of the Schematic Logic Probe(TM) (SLP) for probe-less system debug. Schematic Logic Probe(TM) is a software realization of traditional tools used for debug, such as paper schematics and physical probes. SLP(TM) allows design engineers to control and observe electronic system operation via a software configurable schematic of the system's design and a standard IEEE 1149.1 interface.

Systems are growing complex due to higher levels of integration. Use of fine pitch SMT and large pin count BGA packages has reduced accessibility in the system. The design complexity coupled with this reduced physical access has caused dramatic increases in debug time. One method to overcome this problem has been to create a larger 'debug version' of the PCB for prototyping, with added connectors for probe points and logic analyzer access. This method still increases the time-to-market as a second PCB must go through layout, debug and test before production can begin.

"The fact that an engineer must interactively debug an electronic system makes it one of the most expensive parts of complex system design. It's expensive because of the opportunity costs," said Michael Ricchetti, Chief Technology Officer. "Design engineers that are in the lab debugging systems are not designing and adding value (features) to the design. There is no method to 'run the debug overnight' like a simulation job, for instance. It requires the engineer to sit with the prototype, the debug tools and interactively find and fix the bugs. A large part of reducing the debug time is getting the engineer to understand the part of the design being debugged. An engineer cannot fix bugs unless he can understand the system and has a way to observe and control key points within that system. SLP(TM) facilitates this and allows the design engineer to get back to designing."

SLP(TM) cuts down on debug time and increases efficiency by providing a method for full access to the system's logic as well as a method to cross-reference that logic operation to a display of the system schematic. Schematic Logic Probe(TM) facilitates quick and easy analysis, letting engineers debug and isolate prototype design problems or PCB assembly faults. Users will achieve reduced debug time and improved productivity for system bring-up.

Advanced Schematic based Observation and Control

Schematic Logic Probe(TM) is the answer to state-of-the-art IC, system and board debug on designs that require cumbersome paper schematics for debug and test. The SLP(TM) Graphical User Interface (GUI) displays a schematic of the Unit Under Debug (UUD) annotated with observed logic values from device pins. Users can search for devices, nets and easily traverse off-page net references without sorting through pages of paper schematics. SLP(TM) tackles the complexity problem by enabling engineers to select specific portions of the design that they want to debug, combining logic from multiple pages of the schematic into a single view for debug.

SLP(TM) solves the physical accessibility problem by creating "virtual" probes into the system hardware through a standard IEEE 1149.1 interface that can be driven from a PC's parallel printer port. The observed system logic values read in are then annotated on the schematic displayed. Engineers who like to toggle device pins for debug purposes will have an easier time debugging. The user has the ability to change logic values on the schematic, simply by clicking on a device pin or net. These changes in the schematic logic are transferred to the hardware under debug. The schematic is then updated from the resulting logic changes observed throughout the UUD.

SLP(TM) - Core technology

SLP(TM) transfers data to and from the system under debug through the IEEE 1149.1 serial bus. Use of IEEE 1149.1 in the industry has been underutilized over the years for two reasons. The first reason for limited use of IEEE 1149.1 has been it's close association to traditional ATE companies and therefore the thinking has been that IEEE 1149.1 is another type of production test like ICT. In the past, large in-circuit tester companies have been the primary promoters of 1149.1, which fostered this thinking. "Most engineers have only thought of 1149.1 for interconnect test of PCB's, when actually the standard is much more. It's especially useful for performing this type of non-intrusive debug," said CJ Clark, Intellitech CEO, founder and current IEEE 1149.1 Working Group chair. "Yes, you can perform virtual interconnect testing on your in-circuit tester, but that's not all you can do with IEEE 1149.1" Mr. Clark added. The second reason has been the tools on the market have been too difficult for engineers to use. The 'boundary-scan' tools have required the user to become experts in IEEE 1149.1 architectural details, for example, knowing what instructions to load into the IC's and how the boundary-scan cells capture data on the pins. "SLP(TM) doesn't require you to know anything more about IEEE 1149.1 than you know about IEEE 802.3, which is the IEEE standard for Ethernet networking. You browse the web everyday without being an expert in the IEEE 802.3 networking standard. With SLP(TM) you'll be able to 'browse' your system and it's design, just as easily" he added.

    SLP(TM) Logic Probe Features

    --Non-intrusive probing (observe-only) of the PCB or system

    --No limit to the number of nets or pins that are probed
      simultaneously

    --Display indicates values that are being driven by a pin or
      observed by the pin

    --Three-state display showing high, low or Z on three-state pins
      and bi-directional pins

    --Partially intrusive control of logic values on all two-state,
      three-state and bi-directional output pins

    --Programmable test capabilities through interfaces to
      Intellitech's Eclipse Scan Diagnostic System


    SLP(TM) Schematic Viewing Features

    --Reads output of all major PCB Schematic Capture Software

    --Display-by-net. Display all devices connected to a net or bus on
      a single page with a single mouse click

    --Full schematic manipulation. Specify which devices and nets
      appear on a schematic page

    --Full search capability. Search by Net/Bus name or device
      reference designators

    --Device Partial Views. For large pin count BGA's, only selected
      pins needed for debugging will be displayed

    --Find and follow off-page net designators

    --Full Zoom and zoom-to-region capability

    --Full printing capabilities and export to documentation packages

    --Multi-color display based on your design's actual functionality

Pricing and Availability

Engineers can begin 'probe-less' debug for US$1,995.00. SLP(TM) is available now. A full working 30-day trial version will be available for download from the company's web site www.intellitech.com beginning April 28th. Please contact Intellitech Corp at 603-868-7116 press (2 for Sales) or email [e-mail] for more information.

About Intellitech

Intellitech is the technology leader in scan-based debug and test solutions for SoC (System-on-a-Chip), ICs, PCBs and Systems. Intellitech's scan-based solutions enable customers to debug prototype designs and test production quantities without physical probing. These debug, test and analysis tools enable customers to bring products to market faster by reducing prototype hardware verification times. The scan-based strategy enables customers to realize time and cost savings by the re-use of tests through all phases of the product's life, from hardware simulation, through prototype debug, to production test, field service and depot repair. Intellitech has sales and support offices located in Durham, NH and San Jose, CA

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