Intellectual Property Support for New Lattice FPGAs Grows Rapidly -- ispLeverCORE IP For LatticeECP And LatticeEC Devices Can Be Downloaded, Evaluated Without Charge.
HILLSBORO, Ore. -- IP Partners CAST, DCD (Document Content Description) An XML schema language from Textuality, Microsoft and IBM that is implemented as an RDF vocabulary. It supports data typing and schema reuse and is the successor to XML-Data. See XML schema, RDF and XML. And Eureka Provide Additional Support
Lattice Semiconductor Corporation (Nasdaq:LSCC LSCC Lake-Sumter Community College (Florida)
LSCC Lattice Semiconductor Corporation (stock symbol)
LSCC Lawson State Community College (Alabama) ), today announced the immediate availability of several key ispLeverCORE(TM) intellectual property (IP) modules for its recently announced LatticeECP-DSP(TM) and LatticeEC(TM) FPGAs. The initial IP modules available allow users to rapidly complete designs for functions as diverse as Ethernet, Reed Solomon, PCI (1) (Payment Card Industry) See PCI DSS.
(2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). and DMA (1) (Digital Media Adapter) See digital media hub.
(2) (Document Management Alliance) A specification that provides a common interface for accessing and searching document databases. . These modules, along with others that will become available over the coming months, complement the ispLeverCORE Connection IP cores available from Lattice's third party partners, as well as Lattice's free, industry-standard Reference Designs.
"Lattice is excited to provide designers the unbeatable combination of its next-generation ECP (Enhanced Capabilities Port) See IEEE 1284.
1. ECP - Engineering Change Proposal.
2. ECP - Enhanced Capabilities Port.
3. ECP - Extended Capabilities Port.
4. ECP - Extended Concurrent Prolog. and EC FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices and a comprehensive library of IP modules that allows them to quickly design a variety of the most popular application functions," said Stan Kopec, Lattice vice president of corporate marketing. "Effective design tools and IP are now as integral to successful programmable logic design as silicon. Our ispLeverCORE modules are designed to the highest coding standards, and are extensively tested to meet required functionality and performance. These cores are ready-to-use, well-documented, and fully supported by Lattice field and factory engineers," Kopec concluded.
ispLeverCORE IP for LatticeECP(TM) and LatticeEC Devices
The Lattice ispLeverCORE IP products represent a range of rigorously designed and verified solutions that implement standardized functions commonly used in FPGA designs. Evaluation netlists, which allow the IP to be combined and simulated with the user's logic, can be downloaded for free from Lattice's Web site, www.latticesemi.com. IP cores for the LatticeECP and LatticeEC devices that are currently available for download include:
--10/100 Ethernet MAC
--1G Ethernet MAC
--Multi-Channel DMA Controller
--Reed Solomon Encoder & Reed Solomon Decoder
--Block Convolutional Encoder
Additional IP modules that Lattice intends to make available for its ECP and EC devices include DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM.
DDR - Double Data Rate Random Access Memory Memory Controller, FCRAM FCRAM Fast Cycle Random Access Memory
FCRAM Fast Cycle Ram Memory Controller, Viterbi Decoder, Turbo Decoder, and Numerically Controlled Oscillator oscillator
Mechanical or electronic device that produces a back-and-forth periodic motion. A pendulum is a simple mechanical oscillator that swings with a constant amplitude, requiring the addition of energy at each swing only to compensate for the energy lost because of air .
For its LatticeECP-DSP devices, Lattice is developing a range of DSP-oriented IP that utilizes the sysDSP(TM) blocks embedded in the device. IPs that Lattice intends to make available include popular functions such as Finite Impulse Response (electronics, DSP) Finite Impulse Response - (FIR) A type of digital signal filter, in which every sample of output is the weighted sum of past and current samples of input, using only some finite number of past samples. (FIR) Filters and Fast Fourier Transforms (FFTs).
ispLeverCORE Connection IP and Reference Designs for LatticeECP and LatticeEC Devices
In addition to ispLeverCORE IPs, the Lattice Web site includes details of IP cores for the LatticeECP and LatticeEC FPGAs available from Lattice's ispLeverCORE Connection partners: CAST, Digital Core Design (DCD) and Eureka Technology.
The Lattice partners program is designed to allow customers to easily access and integrate approved third-party IP products using Lattice programmable devices. "Partner IP support for our new FPGA families continues to grow rapidly," said Kopec. "We're pleased to continue our partnerships with CAST, DCD and Eureka Technology, and very excited by the increased IP core performance that each has achieved using our new ispLEVER(R) design tool software."
CAST (http://www.cast-inc.com/) IP cores for the LatticeECP and LatticeEC devices include CAN Bus and 1394a functions. DCD (http://www.dcd.pl/) provides a variety of microprocessor and peripheral functions, including 8051 and PIC compatible microprocessors. Eureka Technology (http://www.eurekatech.com.) provides a variety of bus interface functions and a CompactFlash/PCMCIA Host Adapter IP.
Lattice also has free reference designs now available for the LatticeECP and LatticeEC devices to support functions including:
--QDR II SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. Controller
--SDR SDRAM Controller
--I2C Bus Master Controller
--1553 Data Bus Encoder/Decoder
About the LatticeECP-DSP and LatticeEC FPGA Families
Announced June 28, 2004, the LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP products, targeted for high-performance DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. marketplace.
The first available devices, the LatticeECP20/EC20, are in production and shipping to customers. The remaining LatticeECP and LatticeEC devices are expected to sample in the fourth quarter of 2004, with production release scheduled in the first half of 2005.
About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC FPSC Florida Public Service Commission
FPSC Financial Planners Standards Council (Canada)
FPSC Field Programmable System Chip (Lucent Technologies)
FPSC Fundación Promoción Social de la Cultura ) and high-performance ISP (1) See in-system programmable.
(2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. (TM) Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. ), Programmable Analog Chips (PAC(TM)), and Programmable Digital Interconnect (GDX(TM)). Lattice also offers industry leading SERDES See serializer/deserializer. products. Lattice is "Bringing the Best Together" with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act The Private Securities Litigation Reform Act of 1995 (PSLRA) implemented several significant substantive changes affecting certain cases brought under the federal securities laws, including changes related to pleading, discovery, liability, class representation and awards fees and of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, estimates of market size and growth rate, our dependencies on our silicon wafer suppliers and intellectual property providers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeEC, LatticeECP, LatticeECP-DSP, GDX, ISP, ispLeverCORE, PAC, sysDSP and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.