Intel Develops Tera-Scale Research Chips.Experimental Chips Could Bring TeraFLOP (unit) teraflop - 10^12 flops. Intel beat Hitachi to the record of 1.06 teraflops, on 04 Dec 1996, unofficially in Beverton, Oregon, using 7264 Pentium Pro chips. Performance, Terabytes of Bandwidth into Wide Use in Future Computers and Data Centers SAN FRANCISCO San Francisco (săn frănsĭs`kō), city (1990 pop. 723,959), coextensive with San Francisco co., W Calif., on the tip of a peninsula between the Pacific Ocean and San Francisco Bay, which are connected by the strait known as the Golden -- Intel Corporation (company) Intel Corporation - A US microelectronics manufacturer. They produced the Intel 4004, Intel 8080, Intel 8086, Intel 80186, Intel 80286, Intel 80386, Intel 486 and Pentium microprocessor families as well as many other integrated circuits and personal computer networking today described the significant technical challenges that need to be addressed if computing, from personal devices to giant data centers, is to keep up with increasing demand by consumers and businesses for Internet-based software, services and media-rich experiences. In a speech today at the Intel Developer Forum Intel Developer Forum (IDF), is a twice yearly gathering of technologists to discuss Intel products and products based around Intel products. The first IDF was in 1997. There is usually a Spring IDF and a Fall IDF. , Intel Senior Fellow and Chief Technology Officer Justin Rattner Justin Rattner is an Intel Senior Fellow and director of Intel's Corporate Technology Group. He also serves as the corporation's chief technology officer (CTO). He is responsible for leading Intel's microprocessor, communications and systems technology labs and Intel Research. said that during the next decade online software services, hosted by mega data centers with more than a million servers, will allow people to access personal data, media and applications from any high-performance device to play photo-realistic games, share real-time video and do multimedia data mining. This new usage model will challenge the industry to deliver the one trillion floating-point operations-per-second (teraFLOPs) of performance and terabytes of bandwidth. "The rise of mega data centers and the need for high-performance personal devices will require the industry to innovate at every level, from many-core processors to higher-speed communications between systems, while delivering better security and energy efficiency," said Rattner. "Solving these challenges will bring benefits to all computing devices while creating new markets and opportunities for developers and systems designers." Tera-Scale Research Prototype Chips Rattner outlined the importance of three major silicon breakthroughs. He started by revealing the first details of Intel's tera-scale research prototype silicon, the world's first programmable TeraFLOP processor. Containing 80 simple cores and operating at 3.1 GHz, the goal of this experimental chip is to test interconnect strategies for rapidly moving terabytes of data from core to core and between cores and memory. "When combined with our recent breakthroughs in silicon photonics See integrated optics. , these experimental chips address the three major requirements for tera-scale computing - teraOPS of performance, terabytes-per-second of memory bandwidth Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used , and terabits-per-second of I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output capacity," said Rattner. "While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers." Unlike existing chip designs where hundreds of millions of transistors are uniquely arranged, this chip's design consists of 80 tiles laid out in an 8x10 block array. Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but is not Intel Architecture compatible. The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory. The second major innovation is a 20 megabyte SRAM See static RAM. SRAM - static random-access memory memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores. Rattner demonstrated a third major innovation, the recently announced Hybrid Silicon Laser A hybrid silicon laser is a semiconductor laser fabricated from both silicon and group III-V semiconductor materials. The hybrid silicon laser was developed to address the lack of a silicon laser to enable fabrication of low-cost, mass-producible silicon optical devices. chip developed in collaboration with researchers at University of California, Santa Barbara History The predecessor to UCSB, Santa Barbara State College, focused on teacher training, industrial arts, home economics, and foreign languages. Intense lobbying by an interest group in the City of Santa Barbara led by Thomas Storke and Pearl Chase persuaded the State . With this breakthrough, dozens or maybe hundreds of Hybrid Silicon Lasers could be integrated with other silicon photonic components onto a single silicon chip. This could lead to a terabit-per-second optical link capable of speeding terabytes of data between chips inside computers, between PCs, and between servers inside data centers. Intel will work closely with the industry - original equipment manufacturers, independent software vendors and developers - on a number of fronts to make this vision of tera-scale computing a reality and to bring better, more intelligent products to people around the world that are useful to them where they live. More information on these developments and tera-scale computing research can be found at www.intel.com/go/terascale. About the Intel Developer Forum IDF (Intermediate Distribution Frame) A wiring rack located between the MDF (main distribution frame) and the intended end user devices (telephones, routers, PCs, etc.). Cables run from the outside world to the MDF and then to the IDFs. See MDF and wiring rack. , now in its 10th year, is the premier global technology forum for hardware and software developers to confer on Intel-based platforms, technologies and solutions, and the new usage models they enable. Visit www.intel.com/idf for more information. Intel, the world leader in silicon innovation, develops technologies, products and initiatives to continually advance how people work and live. Additional information about Intel is available at www.intel.com/pressroom. Intel, the Intel logo, Centrino, "Intel. Leap ahead.," "Intel. Leap ahead." logo, Intel Viiv and Intel Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others. |
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