Intel's CEO reveals new bus architecture to be implemented in upcoming Pentium II microprocessor; new implementation addresses bandwidth "valleys of death".

HOUSTON--(BUSINESS WIRE)--April 9, 1997--Intel Corporation CEO Andrew S. Grove outlined today that the Dual Independent Bus (DIB) architecture will be implemented in the Pentium(R) II microprocessor, which will be formally introduced in May.

Speaking to an audience of information technology managers at Compaq's "Innovate" conference, Grove described how the Dual Independent Bus architecture will dramatically improve the ability of the core processor to exchange data with memory subsystems. "Intel's microprocessor performance continues to increase at a phenomenal rate. The Dual Independent Bus architecture allows total system performance to scale with microprocessor performance," Grove said.

Valleys of Death

Grove described the bandwidth bottlenecks in current PC platforms as bandwidth "valleys of death" that limit the output and performance of the microprocessor. "Processor performance alone is not enough," he told the attendees at Compaq Computer Corp.'s Innovate conference. "We must address two 'valleys of death,' namely, the processor-to-memory and processor-to-graphics bus bandwidth bottlenecks."

The introduction of Pentium II processor systems later this quarter with the DIB architecture and the addition of a new feature called the Accelerated Graphics Port (AGP) later this year will address these bandwidth bottlenecks. Collectively, these technologies will provide performance and bandwidth that will scale with Intel processors, which are expected to reach clock rates beyond 500 MHz by the year 2000.

The Visual Connected PC Vision Demonstrated

Grove then went on to introduce the next step in business computing, the Visual Connected PC. The Visual Connected PC consists of a minimum of a Pentium II processor with its Dual Independent Bus architecture, MMX(TM) technology, broad use of the Internet, manageability capabilities, graphics through AGP, and 100 Mbit Ethernet networking interface.

Throughout his presentation, Grove demonstrated the visual computing capabilities as well as the manageability features of a wide range of visual, connected PCs. These technology demonstrations included: -0-

-- A 300 MHz Pentium II processor workstation performing solid

modeling.

-- Real-time 3D rendering on both a 300 MHz and 500 MHz Pentium

II processor-based workstation

-- Web-based manageability of Net PCs using LANDesk(R)

Configuration Manager.

-- A 266 MHz Pentium II processor-based NetPC running Java

applications natively.

-- A 166 MHz Pentium Processor with MMX technology-based notebook

being utilized to transact business visually over the Internet. -0- Dual Independent Bus Architecture = Improved Memory Bandwidth Performance

Grove also provided technical details on how greater bandwidth will be achieved. The Dual Independent Bus architecture was first implemented in the Pentium Pro processor and will continue with the Pentium II processor. The bus architecture dramatically improves the ability of the core processor to exchange data with the memory subsystems over processors with a single bus system like the Pentium processor.

Two buses make up the Dual Independent Bus Architecture: the L2 cache bus and the processor-to-main-memory system bus. The single dedicated L2 cache on the Pentium II processor operates twice as fast as the L2 cache on a Pentium processor. The pipelined system bus enables simultaneous parallel transactions instead of singular sequential transactions. Together these Dual Independent Bus Architecture improvements offer up to three times the bandwidth performance over a single bus architecture processor. In addition, the Dual Independent Bus architecture supports the evolution of today's 66 MHz system bus to a 100 MHz system bus within the next year.

The Pentium II processor and the Dual Independent Bus Architecture will be housed in a new package technology called the Single Edge Contact (S.E.C) cartridge. This new cartridge package and its associated "Slot 1" infrastructure provide the headroom for future high-performance processors and enable the broad availability of Pentium II processors.

AGP = Improved Graphics Bandwidth Performance

By year's end, the Accelerated Graphics Port will make its debut in Pentium II processor-based systems, enhancing visual computing by providing greater memory bandwidth to the graphics subsystem. The AGP interface is a specification for the PC platform that will enable new levels of 3D performance and realism on mainstream PCs. AGP has achieved considerable industry support, and initial systems will be available toward the end of this year. AGP is an industrywide specification driven by Intel.

Intel, the world's largest chip maker, is also a leading manufacturer of personal computer, networking, and communications products. Additional information is available at www.intel.com/pressroom .

CONTACT: Intel Corp.

Howard High, 408/765-1488

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