Integrated Circuit Systems Announces Low-Jitter SAW-Based Clock Translators for OC-192 and GbE with FEC Ratio Support.

Business Editors/High-Tech Writers

WORCESTER, Mass.--(BUSINESS WIRE)--March 14, 2003

-- Optical Network Clock Generators Deliver OC-192 Performance from 9x9 mm Module

-- SAW Based PLL Provides LVPECL Output Clock Up to 700 MHz With (less than) 0.5ps rms Jitter

-- Frequency Translation Capabilities Include FEC Support And Jitter Attenuation

Integrated Circuit Systems (NASDAQ: ICST) announces the release of the new M2006-02 and M2006-12 FEC clock generator PLLs (Phase Locked Loops). Both of these new devices generate a very low-jitter reference clock for high-speed optical data transmission applications. The devices support 10GHz optical link requirements and provide FEC clock translation.

The devices integrate a high performance Phase Locked Loop (PLL) with a low noise Voltage Controlled SAW Oscillator (VCSO). An embedded VCSO provides the high "Q" needed for reference jitter attenuation and stable operation in the digital system environment. Output jitter is less than 0.5 pico-seconds rms at frequencies up to 700MHz. Both the CMOS PLL circuit and the VCSO's SAW (Surface Acoustic Wave) delay line device are packaged together in a 9 x 9mm surface mount package.

The M2006-02 is ideally suited for line card and optical module applications as the optical transmit or framer reference clock. Input selection pins are used to set the input-to-output frequency translation ratio, using pre-programmed lookup table values. Supported ratios include common FEC (Forward Error Correction) or Digital Wrapper multiplication ratios, including 255/236, 255/237, 255/238, and 255/239 for bit stuffing, as well as the inverse of these ratios for de-stuffing.

The M2006-12 includes an Automatic Protection Switching (APS) function ideal for line cards that use redundant clocking. Upon input clock reselection, the APS function enables the PLL to relock without corrupting the transmitted optical stream. The APS function assures Belcore GR-253-CORE compliance during reference reconfiguration.

Either device can be ordered with one of several frequencies, such as 622.08MHz for OC-48 or OC-192, 669.3266MHz for OC-192 FEC, 625MHz for Gigabit Ethernet, and other frequencies up to 700MHz.

Both the M2006-02 and M2006-12 include the following features:

-- Forward and inverse FEC multiplication ratios are

pin-selectable

-- Support for active switching between inverse-FEC and non-FEC

clock ratios (same output frequency)

-- Support for input reference and VCSO frequencies up to 700MHz,

and support for loop timing modes

-- Output jitter less than 0.5 pico-seconds rms

-- Single 3.3V power supply

-- Small 9 x 9mm SMT Package

About ICS:

Integrated Circuit Systems, Inc. is a leader in the design, development and marketing of silicon timing devices for communications, networking, computing and digital multimedia applications. The Company is headquartered in Norristown, PA, with key facilities in San Jose, CA; Tempe, AZ; Worcester, MA and Singapore. For more information, visit the ICS website at: www.icst.com.

(C)2003 Integrated Circuit Systems, Inc. All rights reserved. All company and product names are trademarks or registered trademarks of their respective owners.