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Insight Memec Ships Entry-Level Serial I/O Design Kit for Virtex-II Pro -- Industry's Most Widely Used FPGA for High-Speed Serial Design.


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, Calif.--(BUSINESS WIRE)--Nov. 12, 2003

New Kit Coupled with Reference Designs and Workshops Enable Low

Cost, Easy Deployment of Xilinx 3.125 Gbps Serial Transceiver

Technology

Insight Memec and Xilinx Inc. (NASDAQ NASDAQ
 in full National Association of Securities Dealers Automated Quotations

U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on
:XLNX) today announced the immediate availability of a multi-gigabit serial I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output.

I/O - Input/Output
 design kit designed to make it easy for customers to start using the Xilinx Virtex-II Pro high-speed serial I/O technology. Based on the Memec Design Virtex-II Pro FG456 P4 development board, the new design kit includes two reference design examples along with a step-by-step tutorial workbook. Insight Memec also offers an introductory one-day, hands-on workshop across North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere.  to further accelerate designer's multi-gigabit serial I/O expertise.

"From PCI Express A high-speed peripheral interconnect from Intel introduced in 2002. Note that although sometimes abbreviated "PCX," PCI Express is not the same as "PCI-X" (see PCI-SIG and PCI-X for comparison). As a result of the confusion, "PCI-E" or "PCIe" is the accepted abbreviation.  in PCs to multi-gigabit serial backplanes in high-end communications systems, system designers are radically adopting serial technology to lower overall system cost while increasing performance," said Per Holmberg, director of Virtex Solutions Marketing at Xilinx. "This design kit from Insight Memec allows our mutual customers to instantly validate their serial designs without making a large upfront investment."

"The low cost serial I/O design kit provides an excellent introduction to the growing use of multi-gigabit serial links," said Jim Beneke, director of technical marketing at Memec. "Feedback from our one-day, hands-on Multi-gigabit Serial I/O Design Workshop has been outstanding. Customers feel much more confident with this technology after they go through the design process and can see their application running in hardware."

Based on the Xilinx developed Aurora protocol, currently licensed to more than 1,000 individuals, the two reference designs included in the serial I/O kit The I/O Kit is an open-source framework in the XNU kernel that helps developers code device drivers for Apple's Mac OS X operating system. The I/O Kit framework was originally introduced as part of Apple's Rhapsody operating system that later became Mac OS X, and shared no  show designers how to easily implement a chip-to-chip, and board-to-board serial links. Running at 2.5 Gbps, the Aurora 401 design demonstrates a single channel link, while the Aurora 804 design introduces the use of channel bonding Increasing transmission speed by spreading the data over two or more lines. Bonded analog modems use two analog telephone lines to double transmission capacity, splitting data into two streams of 56 Kbps. In addition, if one modem fails, the transmission continues with the other modem.  to obtain a 10 Gbps aggregate, 4-channel link. The workbook and reference CD included with the kit provides easy to follow instructions for implementing both design examples on the Memec Design Virtex-II Pro FG456 P4 development board.

Xilinx Education Services: Designing with Multi-Gigabit Serial I/O

Customers attending Insight Memec's Multi-Gigabit Serial I/O Design Workshop will receive a coupon for 10% off the Xilinx two-day Designing with Multi-Gigabit Serial I/O course. Customers who attend this intermediate level course will gain insight into utilizing the features of the RocketIO transceiver blocks, such as CRC (Cyclical Redundancy Checking) An error checking technique used to ensure the accuracy of transmitting digital data. The transmitted messages are divided into predetermined lengths which, used as dividends, are divided by a fixed divisor. , 8b/10b encoding, channel bonding, clock correction, and comma detection. Additional topics will include debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users.  techniques, use of the Architecture Wizard, synthesis and implementation considerations, and standards compliance. For a complete description of the Xilinx Education Services course, including a detailed course outline, lab descriptions, and schedules by region, visit: www.xilinx.com/education.

Price and Availability, Workshop Registration

Insight Memec's serial I/O design kit is available now for $995. For complete information about the kit and the Multi-Gigabit Serial I/O Design Workshops, visit www.insight.na.memec.com/x-fest2003 or dial 888-488-4133 ext. 920.

About Insight Memec

Insight Memec is a member of The Memec Group, the world's leading distributor of proprietary advanced-technology semiconductors. Insight Memec focuses its line card on leading semiconductor companies, allowing their sales team and field applications engineers to maintain superior product knowledge and create demand for supplier partner goods. The company's value-added services, design expertise, inventory management, logistics, and e-business tools ensure that customers receive the products they need, when and where they need them. For more information, visit http://www.insight.na.memec.com.

About Xilinx

Xilinx is the worldwide leader in complete programmable logic See PLD.  solutions. For more information, visit www.xilinx.com.
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Publication:Business Wire
Geographic Code:1USA
Date:Nov 12, 2003
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