Inovys Accelerates Design Validation of Complex SOC Devices with the Introduction of SpeedScan(TM) and SpeedMap(TM).PLEASANTON, Calif. -- Inovys Corporation, the leader in the convergence of semiconductor design and test, introduced today, SpeedScan and SpeedMap, the latest addition to the Inovys suite of Design For Test (DFT DFT - discrete Fourier transform ) analysis tools for advanced semiconductor devices. A unique combinational toolset, SpeedScan and SpeedMap use AC Scan techniques for identifying path delay and transition delay faults on complex System On Chip (SOC) devices. These new tools enhance customers' ability to analyze device performance by individual circuit element, achieve device performance characterization using AC Scan, and to identify and diagnose diagnose /di·ag·nose/ (di´ag-nos) to identify or recognize a disease. di·ag·nose v. 1. To distinguish or identify a disease by diagnosis. 2. design problems faster. Accelerating the design validation process enables customers to achieve a faster path to production. New complex SOC devices using nanometer One billionth of a meter. Nanometers are used to measure the wavelengths of light. See angstrom and metric system. processes exhibit more than simple stuck-at fault A Stuck-at fault is a particular fault model used by fault simulators and Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. models. AC Scan patterns are being deployed in both engineering and production for at-speed testing. However, identifying the source of speed related problems on devices that contain millions of gates continues to be a challenge for engineers. SpeedScan and SpeedMap enables datalogging from inside the device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain Scan chains are a technique used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. A special signal called scan enable is added to a design. . Therefore, the challenge of resolving speed related problems is significantly simplified. "Keeping pace with Moore's Law "The number of transistors and resistors on a chip doubles every 18 months." By Intel co-founder Gordon Moore regarding the pace of semiconductor technology. He made this famous comment in 1965 when there were approximately 60 devices on a chip. continues to challenge our customers," said Colin Ritchie, vice president of marketing, Inovys Corporation. "SpeedScan and SpeedMap are powerful tools for design debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. and device performance analysis which helps our customers meet these challenges. This enables customers to complete the design validation of their leading-edge devices faster, which accelerates their time to volume production." You can learn more about SpeedScan, SpeedMap, and other Inovys products during ITC ITC (Brit) n abbr (= Independent Television Commission) → Fernseh-Aufsichtsgremium ITC n abbr (BRIT) (= Independent Television Commission) → week in Austin, TX November 8-10, 2005. Visit www.inovys.com to arrange your private demonstration. About Inovys FlopPlot(TM) and SpeedMap A suite of software analysis tools that display multiple views of device failures, FlopPlot uniquely links a chip's failure data with its design hierarchy and layout. FlopPlot gives users the ability to efficiently manage large volumes of failure data and convert it into easy to understand formats and graphical displays. SpeedMap is the latest addition to this growing family of tools. The powerful FlopPlot suite of tools enable DFT, test and FA engineers to quickly identify and resolve failures in even the most complex devices that contain millions of gates. About Inovys Corporation Inovys Corporation is leading the revolution in semiconductor design and test convergence, providing customers with innovative test solutions for design debug, failure analysis, production and yield management. The Company provides integrated test systems for advanced System on Chip (SoC) devices used in computing computing - computer , consumer and communication applications. Inovys provides a comprehensive test suite that enables semiconductor companies to reduce design debug from weeks to hours, lower production test costs by a factor of four and support real-time yield enhancements with unique failure analysis tools. Additional information is available at www.inovys.com. FlopPlot, SpeedScan and SpeedMap are trademarks of Inovys Corporation. |
|
||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion