Incentia Announces Enhancements to Timing and Synthesis Software for Nanometer Designs; TimeCraft, DesignCraft, and DesignCraft Pro Are Now Ready for 90-Nanometer Design.SANTA CLARA Santa Clara, city, Cuba
Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif. -- Incentia Design Systems, Inc., an EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. company in the timing and synthesis market, today announced the availability of the 2005.05 release of its timing and synthesis software products -- TimeCraft(R), DesignCraft(R), and DesignCraft Pro.
The release improves runtime, capacity and quality across the board, when compared to last year's (2004.10) release. In addition, the release adds several advanced timing sign-off features for 90-nanometer designs and strengthens low power synthesis and analysis capabilities to reduce chip area and power consumption.
"We have made significant enhancements to the performance, runtime and capacity in this release to address 90-nanometer design issues," said Arthur Wei, Vice President of Operations, Incentia. "These improvements match our goal to offer our customers the best-of-the-class timing and synthesis software."
What's New: 90-Nanometer Features, Runtime Speed Up, Capacity & Quality Improvements
Static Timing Analysis
Incentia's TimeCraft static timing analyzer continues to maintain its performance lead and adds advanced timing sign-off features for 90-nanometer designs. Compared to the previous major release, it achieves a 2X runtime speedup and 15% memory usage reduction on average. TimeCraft is enhanced with an 'Image Save & Restore' feature that decreases design import time and a multi-task capability feature to speed up multi-corner analysis. More significantly, the release now includes advanced nanometer timing sign-off features, such as automatic PLL PLL - phase-locked loop clock latency detection, location-based on-chip-variation analysis to resolve timing accuracy issues due to 90-nanometer design process variations, and a new signal integrity analysis option.
Logic Synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL.
Incentia's DesignCraft logic synthesis software improves performance and low power synthesis. This new release achieves a 10% area reduction and a 2X runtime speedup on average, when compared to the previous release. Its low power synthesis is further enhanced through aggressive power and clock gating logic minimization using Incentia's global boolean optimization technique. Its built-in power analysis completely covers dynamic, internal and leakage power. Moreover, its DFT DFT - discrete Fourier transform synthesis achieves 30% runtime speedup. The release targets designs requiring aggressive chip area and power reduction.
Incentia's DesignCraft Pro physical synthesis software achieves a 2X runtime speedup on average with an improved placement engine and timing convergence algorithms. The leakage power optimization is greatly enhanced so that up to an 80% leakage power saving can be realized. The floorplan features are enhanced with improved macro and IO placement capabilities.
Price and Availability
Incentia's 2005.06 release is available now on Sun Solaris (32-bit and 64-bit), Linux (32-bit and AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. 64-bit), and HP (32-bit and 64-bit) platforms. For pricing information, please contact Incentia.
About Incentia Products
Incentia offers advanced complete timing and synthesis solutions to address the ever-growing design challenges in performance, runtime, and capacity for multi-million-gate, nanometer SoC designs.
TimeCraft is a full-chip, gate-level static timing analyzer (STA), offering fast analysis speed. Its rich features enable timing verifications at the pre-signoff (ECO E·co , Umberto Born 1932.
Italian writer best known for his novels, including The Name of the Rose (1981). He has also written extensively on semiotics and British and American popular culture. iteration One repetition of a sequence of instructions or events. For example, in a program loop, one iteration is once through the instructions in the loop. See iterative development.
(programming) iteration - Repetition of a sequence of instructions. ) stage and final signoff for all kinds of design applications.
DesignCraft is a complete logic synthesis tool with integrated capabilities for optimizing area, power, timing and design-for-testability (DFT). It produces aggressive area reduction and low power results, with advantages in runtime and capacity.
DesignCraft Pro is a physical synthesis tool that accepts RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; or netlist designs and creates detailed placement. It offers fast turnaround time (1) In batch processing, the time it takes to receive finished reports after submission of documents or files for processing. In an online environment, turnaround time is the same as response time. and allows users to perform physical performance prototyping and physical optimization as well as resolve design closure issues by simultaneously optimizing for timing, area, power, congestion The condition of a network when there is not enough bandwidth to support the current traffic load.
congestion - When the offered load of a data communication path exceeds the capacity. and DFT.
Incentia Design Systems, Inc. is a leading provider of advanced timing and synthesis software that addresses the stringent requirements of runtime, design capacity, timing, area, design-for-testability, power consumption and signal integrity for multi-million-gate semiconductor designs. The company's products are in use at leading fabless IC design, systems, semiconductor and design service companies and have successfully been used to tape out numerous designs in different design applications, such as communications, networking, wireless, chipset, consumer electronics, and multi-media.
Incentia has offices in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. and Hsinchu Science Park Hsinchu Science Park (Chinese: 新竹科學園區; Hanyu Pinyin: Xīnzhú Kē Xué Yuán Qū; Tongyong Pinyin: Sinjhú Ke Syué Yuán Cyu) was established by the government of Taiwan, ROC on December 15, 1980 with investment from the Kuomintang. , Taiwan, as well as distributors in Japan, China, Korea, India and Israel. For more information, please visit www.incentia.com, email firstname.lastname@example.org or call 408-727-8988.
DesignCraft and TimeCraft are registered trademarks of Incentia Design Systems, Inc.
All other trademarks and tradenames are the property of their respective holders.