In-house artwork verification: you can save time and money by taking control of your design verification, if you know a few tricks.

Although artwork verification has been around for a long time, it is only in recent years that the process of verification has moved into the design department. What was once exclusively a task for the fabricator is increasingly becoming standard operating procedure for the design team. There are several reasons for this trend, including an increased focus on DFM and the decreasing cost of verification software. But perhaps none is more of a motivating factor than today's business climate. The ever-present drumbeat of time-to-market forces design teams to find new ways to reduce design cycle-time. In-house verification has proven an effective method.

Fabricators have done a great job in the role of verification specialist. However, the steps required to locate errors, communicate them back to the designer, implement the changes and upload new files are time-consuming, and these delays invariably come at the most critical--if not visible--time in the design cycle, the end.

In-house verification also permits a review of all aspects of the design. Where the fabricator focuses solely on fabrication-related issues, in-house verification can be aimed at the concerns of engineering, assembly and test as well. For example, violations of part proximity or the omission of solder-mask relief on test-point vias are not concerns of the fabricator, but are important to a design's overall success.

An important rule of artwork verification is to verify the actual data used for board fabrication. If checks are run against the design database, which is then used to generate the plotter data, the process is flawed. If Gerber is the fabrication data of choice, then it's the Gerber that should verified.

In order to verify a design you must first define the criterion you wish to verify against. This criterion consists of design rules and values, based primarily on a DFM spec developed in conjunction with manufacturing. A complete spec includes rules for fabrication, assembly and test. Generic electrical rules may be included, but for the most part are design-specific. Once established, the specification is used to build an electronic "rule set." Like the spec, the rule set must be defined based on two variables: design classification and fabricator capability. Because the rule set for a single-sided through-hole PCB is obviously not suitable for verification of a multilayer HDI design, multiple rule sets are required to carry out the applicable checks for a given design type. Similarly, an offshore high-volume fabricator may not maintain the same capabilities as a domestic quickturn fabricator, again requiring unique rule sets.

Although differences in the rule sets are found primarily in the values of the rules (i.e., .02 annular vs. .01), often the rules themselves differ. For example, a rule to verify the presence of paste mask on an SMD's pads is not required for a single-sided through-hole design.

Building a rule set is typically a one-time task, and preferably dialog-driven. Descriptive dialogs can help make a complex rule understandable. Dialogs describe the rule and the user is required to supply only the value (FIGURE 1). Occasional edits to the rule sets are performed to accommodate fabricator process or capability changes, or to add an omitted check you found the hard way. Ideally, the rule sets are documented with an explanation of each rule and a cross-reference to the DFM spec (FIGURE 2).

[FIGURES 1-2 OMITTED]

In order to perform "intelligent" checks of non-intelligent artwork, one must first add intelligence into the artwork. Otherwise, the artwork remains nothing but primitive circles, paths, and polygons, rendering verification nearly useless. To operate, intelligent verification must have the capacity to determine which primitive objects are pins, vias, traces, fills, etc. To accomplish this, the artwork is "searched," either for objects meeting a certain criteria or for matching database objects. The latter performs a level of verification in and of itself, ensuring that the generated artwork shapes, locations, and presence match the database.

Verification can be grouped into four primary categories: electrical integrity, clearance, coverage and constraints.

Electrical Integrity. First, the electrical integrity of your fabrication data must be verified. Are there any shorts or opens in the artwork? Because your design application works with an intelligent database of objects, rules and hierarchy before creating an output based solely on primitive objects, it's not enough to know the database connectivity matches your schematic. You must ensure the artwork does as well. Years ago, engineers would plot each artwork layer and systematically trace connections, building a netlist to accomplish this. That may have been feasible when your design consisted of a couple of hundred connections, but many of today's high net-count designs require a modern approach. Although this approach is quite similar to the one described above, there are two major differences. First, there are no plots to create, and second and most importantly, your ECAD application does it for you. Accurately extracting the connectivity of thousands of nets in a matter of a few seconds, this process builds an "artwork netlist" and compares it against the schematic generated netlist. If discrepancies exist, they are reported and graphically displayed for review.

Clearance. Clearance checks consist primarily of same-layer and layer-to-layer clearance of the following objects: pins, vias, fills, traces, board edge, components, drills, and miscellaneous. Because most clearance checks can also be performed on the design database, artwork violations are seldom found. This does not, however, lessen the importance placed on artwork clearance checks and in the arena of verification, redundancy is welcome.

Coverage and Annular Ring. Some may feel they've built a good board as long as the design is electrically correct, but omit soldermask relief on your BGA pins and that good board instantly becomes an office pinup. Coverage checks are an integral part of artwork verification and consist primarily of the following:

* Check for the presence or absence of one object layer over another.

* If present, how far does one object layer overhang the other?

* Are the two object layers aligned?

Depending on the rule, a violation occurs if an object is absent over another, or if an object is present over another. For example, the presence of paste mask on SMD pads is a pass condition. Alternatively, the presence of paste mask on a through-hole pin is a fail condition. In addition, if presence is a pass condition, a thorough check can examine the amount of overhang of one object layer over another. In FIGURE 3, for example, the presence of soldermask on an SMD pin is required and the soldermask must overhang the land by .003" (Note: Soldermask is a negative layer). Because an annular ring check must first determine whether the object to measure is present, the discussion of coverage and annular ring can be combined.

Constraints. Constraints consist of miscellaneous rules that fall outside the realm of clearance or coverage. Acute angles, floating metal and minimum drill size are examples of constraint rules. Where other rules are user conceived, constraints rules are typically built into the application and the user must only enable the rule and define the value where applicable.

It's understood that artwork verification is primarily aimed at ensuring your design can be manufactured successfully and with high yield. However, ECAD applications that integrate both design and artwork verification provide the added capacity to target design specific concerns, such as electrical or area rules.

Electrical information such as min/max net length or topology rules can be passed to the artwork and intelligently verified. Net rules (rules that apply to specific nets) usually have electrical considerations such as proximity to other nets (i.e., high noise-to-sensitive net clearance) or minimum trace widths that are greater than the fabrication minimum.

Area rules are another artwork check made possible by the presence of design intelligence. Design-specific area rules designate areas of the board in which smaller minimums are allowed. A BGA field is a good example. These special values are applied to accommodate the density of the specific area while still maintaining manufacturing-friendly rules for the remaining board area. Applying such minimums across the entire board could result in lower yield. Without the knowledge of area rules, artwork checks can apply either the fabrication or area rule values to the entire board. The limitation of this approach is evident in either of the two possible results. If the fabrication values are used, the result is a boatload of violations within the area rule. If the area rule values are used, clearances less than the fabrication minimums but greater then the area rule minimums are missed due to the lenient values of the area rules.

While the cost in both time and money associated with building a bad board underscores the need for thorough verification, performing verification within the design department has many additional benefits. A shortened design cycle and the ability to target areas beyond the scope of the fabricator are among these benefits.

Relying upon the fabricator for artwork verification was once the designer's only choice. Today however, armed with a comprehensive and accurate set of rules to cover the broad range of design concerns, an increasing number of design departments now benefit from in-house verification.

LOU SHABABY is the product manager for Intercept Technology's Pantheon product line. He can be reached at [e-mail].