In case you missed it.

Signal Integrity

"PCB Trace Impedance: Impact of Localized PCB Copper Density"

Authors: Gary A. Brist, Jeff Krieger and Dan Willis; [e-mail].

Abstract: Trace impedances are specified and controlled on PCBs, as their nominal impedance value and variations are kev factors in establishing system I/O bus performance. PCB trace impedances are evaluated and controlled during manufacturing using impedance coupon structures. An issue critical to many high-performance I/O busses is that the actual bus impedance is shifted, and the intra-bus variation is larger than measured using the impedance coupons, leading to PCB motherboards being out of specification. Recent work shows that shifts in measured impedances across a PCB laver are correlated to localized changes in copper density within the fabrication panel due to both the motherboard design and the PCB manufacturer's selection of fill pattern and impedance coupon location. Managing the copper density across the fabrication panel through proper coupon design, placement, and copper fill pattern selection is required to minimize impedance shifts between coupons and product. This paper highlights the impact of copper density on PCB trace impedances and provides a BKM (Best Known Method) for managing copper density and designing impedance coupons to minimize impedance shifts and variations that otherwise could lead to out-of-specification impedances on PCB motherboards. (IPC Apex Expo, February 2012)

"A Study of PCB Insertion Loss Variation in Manufacturing Using a New Low-Cost Metrology"

Authors: Chu-tien Chia, Richard Kunze, David Boggs, and Margaret Cromley; [e-mail].

Abstract: Signal integrity analysis has shown that printed circuit board insertion loss is a key factor affecting high-speed channel performance. Determining and controlling PCB insertion loss has thus become a critical production requirement for achieving multi-gigabit per second data rates. The traditional laboratory method of measuring PCB insertion loss is difficult to adopt in high-volume manufacturing (HVM) environments because it requires expensive equipment, while providing very slow throughput times. In this study we assessed the feasibility of implementing a simpler and lower cost process to measure insertion loss. Through the use of a new metrology developed by Intel engineers, we demonstrated it is capable of quickly and accurately measuring PCB insertion loss and is suitable for use in an HVM environment. Applying this method to a first-time study of insertion loss variation in HVM, we measured lot-to-lot loss variation to be ~[+ or -]0.05dB/ inch at 4GHz, (IPC Apex Expo, February 2012)

Solder Joint Reliability

"The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish"

Authors: Julie Silk, Jianbiao Pan and Mike Powers; [e-mail].

Abstract: This paper reports on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages--QFN and TOPS--on PCBs with a NiAu surface finish. Samples were isothermally aged at the equivalent of 0, 2, 7 and 14 years service life. Representative solder joints were cross-sectioned and analyzed using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX) to investigate the evolution of the solder joint morphology as a function of gold content and isothermal aging. IMC thickness was measured. The effect of gold content on the void percentage was studied as well. The results show that if copper is available to dissolve into the solder joint, the AuSn4 IMC from the bulk does not migrate to the interface as a result of thermal aging. The IMC thickness grew with aging as expected; however, with copper base metallization, the IMC was dominated by Cu6Sn5, and with nickel base metallization on both sides of the joint, the IMC was dominated by AuSn4. Voiding analysis showed that thick gold metallization on thermal pads leads to more voiding and larger standoff height. (IPC Apex Expo, February 2012)

Wave Soldering

"Pb-Free Selective Wave Solder Guidelines for Thermally Challenging PCBs"

Authors: Ramon Mendez, Helen Lowe and Ismael Marin; [e-mail].

Abstract: This paper presents the outcome of a study done with a thick, thermally challenging test vehicle wave soldered using a wide range of selective pallet opening sixes. The test vehicle is 3.05mm (0.120") thick with 20 copper layers, including 10 plane layers, and is populated with several PTH component types. Other design variables include pin-to-hole clearance and quantity of plane layers connected to each pin. PCBs were assembled with a Pb-free alloy (Sn-Ag-Cu) and also SnPb as a baseline. A design of experiment was performed to optimize the wave solder process parameters. Then the optimized process parameters were held constant to focus on varying the pallet opening size only. The results for the various pallet opening sizes and their interaction with the other design factors are discussed. (IPC Apex Expo, February 2012)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.